AMD Zen-based 8-core Desktop CPU Arrives in 2016, on Socket FM3

[newtekie1]

The AMD IPC is poor compared to Intel's. AMD compensates for poor IPC by boosting clocks. That generates quite a bit of heat, hence the new chips will run hot.

You talk like AMD has alway has worse IPC, that simply isn't the case. This is an entirely new architecture, we have no idea what the IPC will be like.

 

[xvi]

Don't understand. Intel chips run hot too. Only thing AMD is lagging behind is power efficiency (of course with the argument of IPC). I read somewhere watts rating of AMD is different than Intel.
Correct me if I am wrong.

From what I understand, Intel measures TDP as more of a "real world" figure and AMD measures TDP as a "most power it will ever use under any workload ever".
TDP is more power consumed and doesn't factor in how well the chip can be cooled. (TIM/solder under the heatspreader, for one example). I'm a bit incorrect. I'll just refer to Wikipedia instead.

Side note: I would hate to see HyperTransport disappear, but then again, why use it when you have PCI-E 3.0.

PCI-e has a bit of latency to it, I believe. Not sure if this is still the case for PCI-e 3.0 though.

 

[mastrdrver]

You're forgetting one thing. They're ditching this mess of a modular and super long pipelined CPU. AMD ran into the same issues Intel did with Netburst, which was that pipeline got too long and that even with high clock speeds, branch miss-prediction became a real problem when it came to stalling the pipeline. On top of that, AMD's L2 cache was way too big and slow compared to Intel's smaller L2.

With that said, we know that AMD has reduced the size of the L2 cache per core and this can only help improve latencies. It is also now dedicated per core (or SMT pair, like Intel's CPUs.) If we also assume that AMD have overhauled their core (which they have,) and that any improvement should be significant. I also suspect that 14nm will play a roll in lowering power consumption.

I'm having a little bit of trouble wrapping my head around how that would work. I suspect that FM3 won't be an SoC socket. However it will be like all the others with the PCI-E root complex on the CPU.

Side note: I would hate to see HyperTransport disappear, but then again, why use it when you have PCI-E 3.0.

1) Cache latency will be improved because they're going to an inclusive cache design.
2) Extra pins. You can have extra unused pins for Bristol and have Summit use those extra pins to connect the southbridge through HT or some other interface. Seeing as how Bristol is a SoC and Summit is not, this seems quite clear to me that these CPUs will not be interchangeable on the same board.

 

[Deleted member 67555]

Just to make this easier for those of you confused, having the same socket for the APU and the CPU on one platform will be done just like it is with the Atlon FM2+ x4 860k and the FM2+ A10-7850k etc...

EDIT:
And I'm sure enthusiast board will do both while cheaper boards will be more specific aka..A58, A75, A88X

 

[Aquinus]

2) Extra pins. You can have extra unused pins for Bristol and have Summit use those extra pins to connect the southbridge through HT or some other interface. Seeing as how Bristol is a SoC and Summit is not, this seems quite clear to me that these CPUs will not be interchangeable on the same board.

That's not my point. My point is that even if you did have extra pins and one was an SoC and the other isn't, then how does that work? I see no point because even if you have all of the I/O connections, that works great with Bristol but what about Summit Ridge? No SoC means that SB or PCH-like chipset needs to be on the motherboard. Are you telling me that motherboards are going to ship with chipsets even if Bristol doesn't use them? That doesn't make any sense because it's a waste of die space or motherboard space depending on how you look at it.

If they're not interchangeable on the same board, then why do they use the same socket if the pinning is going to be different? That's my point. You already have all the wasted pins from not having a iGPU. With that said, I have an expectation that FM3 won't be an SoC socket like AM1 is. Consider that with AM1, that all the boards are the same because all the CPUs have the same SB hardware on the CPU. Plus, in a tower I see little benefit for using an SoC unless you're trying to cram everything on a very small motherboard.

So while I understand what you're saying, from a design perspective, it doesn't really make much sense. It's a lot of work to support both so I doubt it will.

 

[psyph3r]

Why stop there ?
32 core 64 thread monstaaaa

Genius often looks crazy to those that don't understand. Do you even know what Direct X 12 does?! do some research.

 

[MikeMurphy]

Don't understand. Intel chips run hot too. Only thing AMD is lagging behind is power efficiency (of course with the argument of IPC). I read somewhere watts rating of AMD is different than Intel.

Correct me if I am wrong.

AMD lags behind in IPC. To compete with Intel, they need to run their chips at higher clock speeds. Higher clock speeds require more power and result in more heat. Sometimes, AMD even runs their chips far beyond their efficiency range.

 

[MikeMurphy]

You talk like AMD has alway has worse IPC, that simply isn't the case. This is an entirely new architecture, we have no idea what the IPC will be like.

Perhaps they built a time machine to make up for the last ten years of their failed R&D and put all the future technologies into these new cores from the future. Or, maybe their shoestring R&D budget allowed them to do 10+ years of R&D in just one year.

I guess it's possible...

 

[MikeMurphy]

You're forgetting one thing. They're ditching this mess of a modular and super long pipelined CPU. AMD ran into the same issues Intel did with Netburst, which was that pipeline got too long and that even with high clock speeds, branch miss-prediction became a real problem when it came to stalling the pipeline. On top of that, AMD's L2 cache was way too big and slow compared to Intel's smaller L2.

With that said, we know that AMD has reduced the size of the L2 cache per core and this can only help improve latencies. It is also now dedicated per core (or SMT pair, like Intel's CPUs.) If we also assume that AMD have overhauled their core (which they have,) and that any improvement should be significant. I also suspect that 14nm will play a roll in lowering power consumption. All in all, I'm expecting a measurable improvement with Summit Ridge.

I'd like to think short pipeline is good, and long is bad, but I think the truth is a bit more complicated.

I've always liked AMD and I hope they bounce back.

 

[mastrdrver]

That's not my point. My point is that even if you did have extra pins and one was an SoC and the other isn't, then how does that work? I see no point because even if you have all of the I/O connections, that works great with Bristol but what about Summit Ridge? No SoC means that SB or PCH-like chipset needs to be on the motherboard. Are you telling me that motherboards are going to ship with chipsets even if Bristol doesn't use them? That doesn't make any sense because it's a waste of die space or motherboard space depending on how you look at it.

If they're not interchangeable on the same board, then why do they use the same socket if the pinning is going to be different? That's my point. You already have all the wasted pins from not having a iGPU. With that said, I have an expectation that FM3 won't be an SoC socket like AM1 is. Consider that with AM1, that all the boards are the same because all the CPUs have the same SB hardware on the CPU. Plus, in a tower I see little benefit for using an SoC unless you're trying to cram everything on a very small motherboard.

So while I understand what you're saying, from a design perspective, it doesn't really make much sense. It's a lot of work to support both so I doubt it will.

I understand what you're saying, but what I'm saying is that it appears that they use the same socket. It's just that Summit Ridge will be (for example sake) 1090fx and Bristol will be 90X. It's possible that they could use two different keys to keep people from putting the wrong CPU in the wrong board. I'm more apt to believe that then that they're interchangeable since Bristol is labeled as a SoC. Though this is an assumption and only time will tell for certain.

The pinning does not need to be different, just certain pins (for the I/O) are not used on a Summit Ridge 1090fx board or are used to connect to the PCH or Southbridge. While on the Bristol Ridge board these same pins are used to connect to the I/O ports. This is not that far fetched. Depending on the CPU the pins have different purposes and are wired differently. Instead of the socket having a fixed pin wiring, it's the CPU (Summit or Bristol, 1090fx or 90x) that determines they're use. This would explain how Styx (ARM K12) and Basilisk (x86) use the same socket.

I'd like to think short pipeline is good, and long is bad, but I think the truth is a bit more complicated.

I've always liked AMD and I hope they bounce back.

The pipeline determines the clock speed. Short ones have a lower clock speed (fewer calculations per second) while longer ones have higher clock speeds. Long pipelines are not bad as long as you don't stall a core which has been one of the problems with the Bulldozer uarch. The scheduler (from what I've read) can't keep the cores busy so you end up wasting power. If you have a branch prediction miss, it just makes the whole thing worse because the core has to wait for the correct information to be fetched.

 

[TopHatKiller]

I wish everyone would stop making uniformed b.s. guesses. Why assume that summit-ridge, if it exists, is competitive with mainstream intel chips rather then server-derived ones? Just because the rumored socket is the same as a mainstream chip? That's nuts. An octo core Zen should trash any quad intel - and that's not speculation - that's a.... oh.

 

[newtekie1]

Perhaps they built a time machine to make up for the last ten years of their failed R&D and put all the future technologies into these new cores from the future. Or, maybe their shoestring R&D budget allowed them to do 10+ years of R&D in just one year.

I guess it's possible...

They'll have 5 years of development on Zen by the time it is released. They've also brought on one of the best CPU designers around. He was with AMD through Athlon XP into Athlon 64, bringing AMD to the point of actually outperforming Intel even at the highest levels. He then left and went to Apple, turning their mobile processors around and creating the A4, A5, and A5X, allowing apple to lead the mobile market.

Bulldozer was designed by a computer. Then every release after that has just been optimizing to fix how in-efficient the computer made the architecture.

So yea, any thing is possible.

 

[cadaveca]

For gaming users, AMD is about to become a bit more relevant, IMHO, since many devs are already using AMD hardware on the consoles on a daily basis, not Intel. So games are designed to use what AMD offers, and might need "porting" to use Intel hardware, which might flip the performance balance over to AMD.

Of course, that's my ideal scenario, but while just an ideal, it is definitely possible that AMD took a bit of time ignoring the general user, all the while actually being more focused, but in a different direction than most might have imagined.

 

[CyberBuddha]

They'll have 5 years of development on Zen by the time it is released. They've also brought on one of the best CPU designers around. He was with AMD through Athlon XP into Athlon 64, bringing AMD to the point of actually outperforming Intel even at the highest levels. He then left and went to Apple, turning their mobile processors around and creating the A4, A5, and A5X, allowing apple to lead the mobile market.

Bulldozer was designed by a computer. Then every release after that has just been optimizing to fix how in-efficient the computer made the architecture.

So yea, any thing is possible.

Could you please tell me the name of that chip designer? I would like to know more about him... thank you

 

[newtekie1]

Could you please tell me the name of that chip designer? I would like to know more about him... thank you

Jim Keller

 

[GoFigureItOut]

I saw another picture about the Zen core and it was stated that it will be using FM4

 

[mastrdrver]

According to the Financial Day Report that happened last week, the socket will be AM4 and it appears that Zen will initially be reserved for servers and workstation 1 socket setups.

 

[Caring1]

According to the Financial Day Report that happened last week, the socket will be AM4 and it appears that Zen will initially be reserved for servers and workstation 1 socket setups.

AM4 implies it may be suitable for FX Processors, if the socket is backwards compatible.
More likely to be FM4 at this stage and low power.

 

[Aquinus]

AM4 implies it may be suitable for FX Processors, if the socket is backwards compatible.
More likely to be FM4 at this stage and low power.

I suspect the different sockets depends on the number of DRAM channels and PCI-E lanes, since "Xen" CPUs will have the PCI-E root complex on the CPU instead of the "north bridge", so more lanes means more pins (unless you're using a PLX bridge chip of course.) I suspect Xen's architecture will end up on most of AMD's CPUs if it proves to be a success. What I'm seeing is the same thing Intel is doing; skt1150, Intel's mainstream platform, goes up to quad core, sports an iGPU, and supports 2 memory channels, which sounds exactly like AMD's APU lineup (albeit slower CPUs, but same general idea.) Then you have skt2011-3, Intel's HEDT and server platform, spots 40 PCI-E lanes instead of 16 (which requires over twice as many pins as skt1150,), you have quad-channel memory (which doubles the number of pins associated with DRAM), and you have bigger dies that can consume more power so you add pins for power delivery. So you have this situation where skt2011-3 by virtue almost twice as many pins as 1150 because it can have twice of just about everything (sans the iGPU, which really doesn't take much pinning.)

So with that said:
If FM4 is to 1150, then AM4 is to 2011-3.

I say this because if "Xen" is claimed to have a huge number of PCI-E lanes on chip, then I suspect that AM4 will have a very different pinning than we've seen in the past which wouldn't jive nicely with how APUs have had a limited number of PCI-E lanes (22 on FM4 coming up I think). The simple point really is that this is AMD (like Intel) making a distinction between the consumer products and the high-end/server market products. They've really just tuned the lineup with the market in my opinion. More pins = more traces = more money and there is no need to make a mainstream platform expensive if the company is considering their bottom line.

It really comes down to market segmentation. Generally speaking, consumers will be happy with an iGPU and fast cores... and generally speaking, servers and workstations will require either discrete graphics or none at all (minus something super low power and weak) and more cores. But either way, Xen (if half decent,) will find its way into both markets like Bulldozer did. I think that's a given.

 

[peche]

Cannonlake/10nm,

this will be intels win note....

 

[mastrdrver]

AM4 implies it may be suitable for FX Processors, if the socket is backwards compatible.
More likely to be FM4 at this stage and low power.

Was that said in the Q&A session? If not, then AM4 means AM4 and nothing else just like the official slide says. As I stated before, even David Kanter questions whether Zen will show up in the APU because the slide seems to limit it to the FX CPUs.

 

[Corey]

Well, AM1 died quickly...

Pitty I wanted to make a fan less HT PC with one of them.

 

[Dent1]

Pitty I wanted to make a fan less HT PC with one of them.

Vampires, vampires everywhere. Awaking a 6 month old thread!

 

[mroofie]

Damn this thread still going