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- May 8, 2016
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System Name | BOX |
---|---|
Processor | Core i7 6950X @ 4,26GHz (1,28V) |
Motherboard | X99 SOC Champion (BIOS F23c + bifurcation mod) |
Cooling | Thermalright Venomous-X + 2x Delta 38mm PWM (Push-Pull) |
Memory | Patriot Viper Steel 4000MHz CL16 4x8GB (@3240MHz CL12.12.12.24 CR2T @ 1,48V) |
Video Card(s) | Titan V (~1650MHz @ 0.77V, HBM2 1GHz, Forced P2 state [OFF]) |
Storage | WD SN850X 2TB + Samsung EVO 2TB (SATA) + Seagate Exos X20 20TB (4Kn mode) |
Display(s) | LG 27GP950-B |
Case | Fractal Design Meshify 2 XL |
Audio Device(s) | Motu M4 (audio interface) + ATH-A900Z + Behringer C-1 |
Power Supply | Seasonic X-760 (760W) |
Mouse | Logitech RX-250 |
Keyboard | HP KB-9970 |
Software | Windows 10 Pro x64 |
It may be simply issue of "not-scaling" case (not all things scale the same), also more density = more focus heat, so it's not always good idea to go max. density all the time.Is Blackwell transistor count accurate there? Blackwell dies seem to have essentially less transistors per SM. Looking at what has been revealed that does not quite make sense. Blackwell should have slightly more transistors. Did they cut down somewhere? Cache?
Lastly, since NV marketed "AI" as shader part (with M$ throwing it's support behind this on DirectX side), it's possible tensor cores are being shifted from seperate units to actual workload on shaders (a.k.a. Cuda Cores).
In short, each shader/cuda core may be capable of doing tensor operations (provided by Async compute ).
I'd speculate that to get full capability of "old hardware tensor" from Ada/Ampere gen, an SM level context limit is needed (analogy : CCs are pretty dumb, like car engine - by itself it just can't go anywhere, wheels/axels/steering/etc. are required).
^This is 100% guesswork at this moment, since we don't have a public whitepaper on RTX 50 series (GB202/203/205/206/207) yet.