Core Configurations of Intel Core Ultra 200 "Arrow Lake-S" Desktop Processors Surface

[Dr. Dro]

Correct, and I may add that the complexity of implementing SMT in the pipeline has grown greatly with ever more superscalar CPU designs. Not to mention the biggest problem; all the security issues, which requires lots of constraints for the designers to avoid. Thirdly, there is also the fact that modern CPUs have much more capable front-ends, which are better and better at keeping the execution units saturated. This was originally one of the core motivations of SMT, but going forward the potential gain here is going to shrink relatively speaking.


If you're talking of architectural engineering decisions, then I disagree. Their designs have generally been held back 2-3 years due to production issues, which probably still have some lasting delays. When it comes to their production however, there has been lots of bad decisions…

As to a "clean room" design, I doubt any of big CPU designers will start that much from scratch, but they do however have to make the big design decisions in the very beginning of the design process, like how threading will work, how cores are interacting etc., as all other design decisions are resulting from that, although they probably don't have the resources to redesign and finetune every tiny part of the CPU design in the first try. So deciding to ditch SMT certainly was done early on, but I would expect them to need a few "attempts" to fully break free from all the design constraints and unleash new levels of IPC.

Looking forward, there will be a lot of advancements in superscalar execution. I know Intel are looking into strategies to lessen the impact of branch mispredictions and avoid pipeline stalls and flushes. I believe some of this was supposed to show up in Meteor Lake, but I haven't studied whether it is and the success of it. But over the next generations, we should expect there to be significant gains.


Just for the sake of being correct, Rocket Lake wasn't a regression in terms of overall performance, it offered ~19% IPC gains and similar clocks, but sacrificed 2 cores vs. Comet Lake, which leads to people thinking it was inferior. Rocket Lake which was a "backport" of Ice Lake to 14nm was greatly held back by this "inferior" node. The whole family is called "Sunny Cove", with Ice Lake being released in 2019 (server only, very limited availability), followed by Tiger Lake which was a small architectural improvement. Rocket Lake surprisingly seems to be a derivative of Ice Lake-S(never finalized) rather than Tiger Lake, I assume because Tiger Lake never was designed for this purpose and it was much quicker to backport Ice Lake-S instead.

Apologies I should have been more specific, I'm referring to gaming performance. Most games still favor the i9-10900K over the 11900K.

 

[AnotherReader]

Correct, and I may add that the complexity of implementing SMT in the pipeline has grown greatly with ever more superscalar CPU designs. Not to mention the biggest problem; all the security issues, which requires lots of constraints for the designers to avoid. Thirdly, there is also the fact that modern CPUs have much more capable front-ends, which are better and better at keeping the execution units saturated. This was originally one of the core motivations of SMT, but going forward the potential gain here is going to shrink relatively speaking.


If you're talking of architectural engineering decisions, then I disagree. Their designs have generally been held back 2-3 years due to production issues, which probably still have some lasting delays. When it comes to their production however, there has been lots of bad decisions…

As to a "clean room" design, I doubt any of big CPU designers will start that much from scratch, but they do however have to make the big design decisions in the very beginning of the design process, like how threading will work, how cores are interacting etc., as all other design decisions are resulting from that, although they probably don't have the resources to redesign and finetune every tiny part of the CPU design in the first try. So deciding to ditch SMT certainly was done early on, but I would expect them to need a few "attempts" to fully break free from all the design constraints and unleash new levels of IPC.

Looking forward, there will be a lot of advancements in superscalar execution. I know Intel are looking into strategies to lessen the impact of branch mispredictions and avoid pipeline stalls and flushes. I believe some of this was supposed to show up in Meteor Lake, but I haven't studied whether it is and the success of it. But over the next generations, we should expect there to be significant gains.


Just for the sake of being correct, Rocket Lake wasn't a regression in terms of overall performance, it offered ~19% IPC gains and similar clocks, but sacrificed 2 cores vs. Comet Lake, which leads to people thinking it was inferior. Rocket Lake which was a "backport" of Ice Lake to 14nm was greatly held back by this "inferior" node. The whole family is called "Sunny Cove", with Ice Lake being released in 2019 (server only, very limited availability), followed by Tiger Lake which was a small architectural improvement. Rocket Lake surprisingly seems to be a derivative of Ice Lake-S(never finalized) rather than Tiger Lake, I assume because Tiger Lake never was designed for this purpose and it was much quicker to backport Ice Lake-S instead.

SMT's relative contribution to the die area doesn't increase with the complexity of the rest of the core; both ThunderX3 and the Pentium 4 spent about 5% of their area on SMT. However, both validation time, and crucially, the attack surface for machines hosted in the cloud increase because of SMT. A relatively simple fix would have been for hypervisors to avoid splitting 2 logical threads of one core across multiple customers.