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CPU Database

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Is it like partially disabled? Cache I mean...

-Dan
 
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djbbenn said:
Is it like partially disabled? Cache I mean...

-Dan
Yes it's 512 cache is disabled but it's still a Toledo core, it's not a Manchester.

E6 Revision = Toledo
E4 Revision = Manchester

My 512kb Toledo


1MB Toledo http://img240.imageshack.us/img240/4810/32m28135621za.jpg

True Manchester E4 Revision http://img370.imageshack.us/img370/8854/32m9fc.png

Toledo's have a bigger die then the Manchesters.
 
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I don't think it will be put in, can cause to much confusion. It's still showed as a Manchester core, it's only the revision that's different. They are still basically the same core, with different L2 cache. The bigger die is just because of the cache.

-Dan
 

spectre440

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reposted.
 

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Thanks. ;)

-Dan
 

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no, thank you.
 
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I'll look around... there is mistakes in it. Corrected a few already, it just got a little hard on the head when working on all those cpu's. :)

-Dan
 
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spectre440

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nope. my bad.
he has a newcastle
 

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May be a little late, or already mentioned, but the 754 Newcastle 3400+ is 2.4Ghz 200x12. Not 2.2 as listed.
 
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Seems to be missing several Celeron D processors, especially the socket 478 versions.

According to CPU-Z, I have a Celeron D 320, mPGA-478, 2400mHz, 18x multiplier, 90nm, 1.4v(unsure), 16KB L1, 256KB L2, no L3. The TDP I'm not sure of.

Incidentally, I believe the proper codename for all Celeron D processors is actually Prescott-256, not just Prescott.

I also had a 1700mHz Willamette Celeron, 17x multiplier, 128KB L2, mPGA-478. The rest of the specs I'm unsure of, as it's not usable at the moment.
 
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Some of the Celerons are missing, it's very hard to get every single cpu in there, but we're working on it. The core is a Prescott, but it has 256KB of L2 cache instead of 1024KB, and that's the reason for the "Prescott-256".

-Dan
 

ElPenguino

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it's a modified prescott core, actually...
in more ways than just cache, too.

edit: I almost forgot... the 3x6 and 3x1 celeron Ds are pretty much identical to their 3x5 and 3x0 counterparts, except they have EM64T and XD enabled.
 
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They have less cache, a slower fsb (higher mulitplier in return) and a few less features (HT, NX-Bit in some cases, etc). They are still the Prescott core, just "modified" like you said.

-Dan
 
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Celerons are chips that dont make spec for the P4, their cache is cut, and some features disabled, it depends on the wafer.
 

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very true. case in point my old celeron 2.7 (100x27) clocked up to 3.5 stabily at stock voltage. definatly a p4 with lower clocks.
 
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Albany 2800+M in my laptop. 90nm ofcourse, 1600mhz. 256kb L2
 
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Core 2 Extreme/Duo (Conroes & Allendales) have been added... if anyone knows the die size in mm² for them, please post them here. :)

Edit: Also for Merom, the mobile Conroes. (both 4MB and 2MB versions)

-Dan
 
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Conroes' and Allendales' die size is 143 mm2. Even though Allendale has half the L2, it's still physically on the die, half is just disabled.
 
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Can you send me the link for that information?

-Dan
 

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Thanks Migons.

-Dan
 

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Allendales' transistor count is also 291M.

Although Tom's Hardware says Allendales' transistor count would be 167M and die size 111 mm^2, it's as I said before.

And Athlon 64 3500+ ClawHammer's transistor count is 106M (not 69M). The reason is the same as with Allendale - disabled L2 is still on the die.
 

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Conroe Package

Hello.

I'm a bit confused and I may be mixing ideas/concepts. Even though Conroe package system it is showed everywhere as the FC-LGA4, in this official document by Intel at page 43 they state that Conroe uses FC LGA6 .

Here in this other document at page 37 also states that the processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket.

Thanks in advance.
 
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Yeah they do use FC-LGA6, I'll have to change it. Thanks for bringing that up.

-Dan
 
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