CPU-Z Screenshot of Alleged Intel Core Ultra 9 285K "Arrow Lake" ES Surfaces, Confirms Intel 4 Process

[N/A]

b0 revision is 7nm intel 4 and 3 nodelets, that can be ported to TSMC N3 since it follows the same normalised designing rules. I'm guessing c0 revision 6+8 nonK SKU is 5nm (20A).

 

[theouto]

There are so many leaks for generations so far into the future (core 300 leaking) that I'm somewhat lost as to what intel gen we are currently on.
And they slanted AMD for their naming scheme.

 

[N/A]

The one you should be on the lookout for is nova lake. That is to be completely reworked from the ground up and properly implementing the rentable units, 50% IPC compared to rocket lake or raptor lake, ultra 500 I guess.

And one more thing, intel 4 and 3 seem to be nodelets of 7nm, but tsmc N4 and N3 are full nodes so I don't understand what was intel thinking. They wanted to be king of consolidated around the same metrics but then not so much. I'm overall a little disappointed, we should be getting that high NA and backside power delivery at this point.

 

[AnotherReader]

The one you should be on the lookout for is nova lake. That is to be completely reworked from the ground up and properly implementing the rentable units, 50% IPC compared to rocket lake or raptor lake, ultra 500 I guess.

And one more thing, intel 4 and 3 seem to be nodelets of 7nm, but tsmc N4 and N3 are full nodes so I don't understand what was intel thinking. They wanted to be king of consolidated around the same metrics but then not so much. I'm overall a little disappointed, we should be getting that high NA and backside power delivery at this point.

50% IPC increase at the same clocks is unprecedented for a P core. That would be akin to the uplift from the original Pentium to the Pentium Pro. Do you have a source to backup that claim?

 

[AusWolf]

And one more thing, intel 4 and 3 seem to be nodelets of 7nm, but tsmc N4 and N3 are full nodes so I don't understand what was intel thinking. They wanted to be king of consolidated around the same metrics but then not so much. I'm overall a little disappointed, we should be getting that high NA and backside power delivery at this point.

It's all about you and I having to do some research to see what these node numbers actually mean, while the average consumer thinks they're the same as TSMC N4 and N3. Marketing.

 

[Vincero]

It's all about you and I having to do some research to see what these node numbers actually mean, while the average consumer thinks they're the same as TSMC N4 and N3. Marketing.

To be fair that marketing goes both ways e.g. TSMC 12nm wasn't equal to Intel 12nm. I remember back in the day reading that TSMC/Samsung/GlobalFoundries were some way off the same transistor density as Intel could achieve (and no doubt there probably was some other chip features that were not equal either).
Sure TSMC have 3nm before Intel, Samsung, etc., but that's not to say it will actually be the best example of it - the transistors are usually several times bigger than 3nm for example.
For sure, TSMC are making some chip features smaller, but due to the limits of the metals in use you can only make the size of the components in the chip so small.

What I'm most impressed about is that despite moving to smaller processes, the leakage current is actually being very well controlled - the idle power numbers for example of these chips going down to low single digits whilst having billions of transistors - a while ago there were some who thought this would end up making moving to some smaller processes less desirable.

 

[AusWolf]

To be fair that marketing goes both ways e.g. TSMC 12nm wasn't equal to Intel 12nm. I remember back in the day reading that TSMC/Samsung/GlobalFoundries were some way off the same transistor density as Intel could achieve (and no doubt there probably was some other chip features that were not equal either).
Sure TSMC have 3nm before Intel, Samsung, etc., but that's not to say it will actually be the best example of it - the transistors are usually several times bigger than 3nm for example.
For sure, TSMC are making some chip features smaller, but due to the limits of the metals in use you can only make the size of the components in the chip so small.

Yes, but Joe Consumer doesn't know all this.

 

[close]

I'd rather it started with a 6 and then users can tone it down a notch then it being at 5 and users having to oc it. Well "having", you don't have to do anything, im just saying it's easier to leash a chip then unleash it as an end user.


It doesn't need to. Originally the 13900k launched as a 7900x competitor, and it gave it a thorough spanking.

The stack according to both amd's and intel's naming scheme is i5 13600k vs R5 7600x , i7 13700k vs R7 7700x and i9 13900k vs r9 7900x. Those cpus launched at very similar (actually, besides the 900k, they were identical) MSRPs and names.

Now with the new naming schemes i'm kinda confused about what's what so we have to see

Takes a brave (euphemistically speaking) man to be so confident about how good 13th gen Intel CPUs are these days. Aren't 13900s dying from all that spanking they gave? Live fast die young isn't really a good characterization for a CPU.