IPC has increased per core
How it increases is unknown till it releases
Yes sir.
The more you tell me that, the more I believe. Faith is starting to grow on me!
God, I've been so wrong. How could I have assumed it had anything to do with tech, when it's all magic! It's something mystical that nobody knows until the truth is revelaed to us by the Lords. The answer is not on the architecture, it's on our faith. Through faith we will be stronger and beat competition!!
No, now seriously.
Pretty much everything has been revealed about the architecture and there's no magic formula. Actual/runtime IPC (as oposed to theoretical IPC) in BD might end up higher than on previous AMD architectures because of 2 main reasons:
1- use of multi-threading.
2- better branch prediction.
Point n. 1 is what we are mostly discussing. How much better is CMT over SMT? AMD will obviously want make you believe it's much much better and so much better in fact that it equals 2 complete cores. I call BS.
Point n. 2 is from where most serious IPC improvement claims come from. Most of the improvements for Sandy came exactly from increased IPC due to better scheduling and branch prediction. Theorerical IPC remains the same as Nehalem after all, and the 2500k can often times match 6 core i7's on threaded apps. Westmere already had much improved front end, and SB supposed an even bigger jump.
Bulldozer does introduce a much stronger branch predictor, but it's still to be seen if it can match or even come close to Intel's, which is its strongest point since Core 2.
It is 4 Complex Instructions per clock per module
The decoders are a fusion of Complex and Simple which is like
What is the difference between
3 Simple Instructions(Phenom II)
to
4 Complex Instructions(FX)
Read the link I posted, please.
At some point you will have to stop posting BS. Istanbul could do 3 simple and 3 complex too and Bd does 4 simple/4complex per module. So does Intel (mixing simple and complex), although differently.