NVIDIA GeForce RTX 5080 Founders Edition

[lexluthermiester]

He's the only one not getting it, even with proof he still won't believe us lol

Irony. Context doesn't seem to to be your strong suit.

The Blackwell lith process is a custom modified 4nm version of the 3N process TSMC is currently manufacturing.

It is known that that process is both different from the process used for RTX4000 AND derived from TSMC 3N.

You're just not following along. You either lack the ability to make the connection or you're just being a troll.

TSMC 3nm node has a 200M+/mm² density.

What part of "customized" do you not understand?

then compare with.. 0% improve arch and perf/$|mm|tr|w and all otherView attachment 383756

If there's no improvement, then why bother changing/customizing it, hmmm?

 

[DemonicRyzen666]

Irony. Context doesn't seem to to be your strong suit.


You're just not following along. You either lack the ability to make the connection or you're just being a troll.

What part of "customized" do you not understand?


If there's no improvement, then why bother changing/customizing it, hmmm?

If you consider 1% "an improvement"

When it could literally be just the margin or error for the tests

IT'S NOT AN IMPROVEMENT~!
Be 0% or 1% it's with in margin of error for the tests on efficiency there for, ZERO IMPROVEMENTS

 

[lexluthermiester]

Good grief.. The Osmium seem to be in abundance.

 

[RUSerious]

https://www.hardwareluxx.de/index.p...rchitektur-und-den-geforce-rtx-50-karten.html

TSMC 3nm node has a 200M+/mm² density.

FWIW. Quoted densities from TSMC, and other, usually are taken from very simple designs (test wafers will simple semiconductors like an ARM core). Actual design densities tend to be lower.

Nvidia always use Custom nodes, but N4P is a 4nm node aka an Enhanced 5nm node.

For large customers, yes. This was true for Apple long before doing so for others. These are only optimizations done for the customer with slightly higher/lower density, low power draw/higher performance, etc. N3 was probably too far out when NVidia was planning Blackwell (years before release). TSMC FinFlex comes in for N3, and should make it even easier to optimize designs, especially for smaller customers. Those options will be baked into the PDK and available to designers via EDA software like Cadence, etc.

 

[EarthDog]

@W1zzard - Can you clarify some things that have been discussed in this thread?

1. Is consumer Blackwell, GB202/203, using the 4N (5nm) process and the same as Ada Lovelace?
2. DATACENTER Blackwell, GB200, uses 4NP based on 4N (5nm) and uses a 'refined' process.
3. Does 4NP have anything to do with 3N/3nm?

EDIT: I see...from the 5090 Review - "At the heart of the GeForce RTX 5090 we are reviewing today is the mammoth 5 nm GB202 silicon...The process is unchanged between the two generations—it's still an NVIDIA-specific variant of TSMC 5 nm EUV, dubbed TSMC 4N."

...but some clarity/confirmation from a reputable source (you w1z!) would be awesome.

 

[W1zzard]

Is consumer Blackwell, GB202/203, using the 4N (5nm) process and the same as Ada Lovelace?

NVIDIA says "same process as Ada", but they also say "4 nanometer", but also "4N NVIDIA Custom Process"

When I asked for clarification they acted dumb, answered a completely different question and said "that's all we can say about the processors"

Back during Ada the conclusion was that it's really a 5 nm process. If it really was 4 nm now or back then, they could easily clarify that without dancing around the words

 

[x4it3n]

FWIW. Quoted densities from TSMC, and other, usually are taken from very simple designs (test wafers will simple semiconductors like an ARM core). Actual design densities tend to be lower.


For large customers, yes. This was true for Apple long before doing so for others. These are only optimizations done for the customer with slightly higher/lower density, low power draw/higher performance, etc. N3 was probably too far out when NVidia was planning Blackwell (years before release). TSMC FinFlex comes in for N3, and should make it even easier to optimize designs, especially for smaller customers. Those options will be baked into the PDK and available to designers via EDA software like Cadence, etc.

Actual design densities tend to be lower in the end yes, but the GB202 density is too low to be based on a 3nm node! And that's what I was trying to explain to lexluthermiester that kept saying Blackwell was based on a 3nm node...

AD102: 125.3M/mm² and 609mm² die size
GB202: 122.9M/mm² and 750mm² die size

TSMC N3 is about ~193M/mm² and can also get closer to ~224M/mm² with an N3P like node, so even if the density is lower on end products the gap is too big to be 3nm. Nvidia are using an N4P like node which is an Enhanced 5nm node, and not a 3nm node.

 

[x4it3n]

Irony. Context doesn't seem to to be your strong suit.


You're just not following along. You either lack the ability to make the connection or you're just being a troll.

What part of "customized" do you not understand?


If there's no improvement, then why bother changing/customizing it, hmmm?

They are using a 4nm node with some process learned from TSMC 3nm. But that is in no case a 3nm node nor a big change at all. The could have gone for a real 3nm node but they chose not to, probably due to lower yields and higher price. They chose to use their Tensor Cores (AI) to "offer more performance" but a N3P like node would have offered better efficiency for sure.

 

[lexluthermiester]

They are using a 4nm node with some process learned from TSMC 3nm.

But that is in no case a 3nm node nor a big change at all.

Except that they've openly stated that it is, so there's that.