PCIe 5.0 makes things even more complicated. Given the memory chip layout, some lanes probably run under the memory chips and/or other lanes. This is quite unfavourable because these wires require a specific geometry (distance to ground, to other lanes etc).
Well there is a good amount of layers on the PCB for that but I agree PCI Gen5 doesn't make it easy. Basically 90% of the IOs have a very high bandwidth, which is actually not so frequent.