Radeon HD 5890?

[Monkey_Business]

Will a Phenom II X4 965 @ 3.4 GHz "choke" on a single HD 5870? It it absolutely imperative to have a Ci7 @ 4.5 GHz if you want to properly use the HD 5xxx series graphics cards without a severe bottleneck?

Think of trying to run Two GTX 295's in SLI on a Pentium 4.

 

[erocker]

Will a Phenom II X4 965 @ 3.4 GHz "choke" on a single HD 5870?

No.

It it absolutely imperative to have a Ci7 @ 4.5 GHz if you want to properly use the HD 5xxx series graphics cards without a severe bottleneck?

No.

Think of trying to run Two GTX 295's in SLI on a Pentium 4.

Yes, bottleneck.

 

[btarunr]

at this point no one knows, though there are rumors of "trillian" floating around somewhere if your into that sort of thing

"Trillian" is Radeon HD 5870 Eyefinity6.

 

[jessicafae]

I don't know why no one has ever brought this up, but ATI never released an official die shot of cypress. They have only officially released architecture block diagrams. And the leaked die image (below from this post) actually has 2x16x16x5 shaders (2560sp, note the 16 rows on each side of 4x4 blocks) not the 2x10x16x5 as in the official block diagram.

I know many people disregarded this leaked die shot as fake back in October 2009, but since ATI has not released an official die shot, it does raise the question of whether this really is cypress and if even 5870 is a partially disabled chip with the 5890 being the full chip with 512 SIMD engines with 2560 total shaders.

 

[btarunr]

Those extra physical shaders are to help with harvesting. They'll never all be enabled, as the architecture won't permit that. They help serve as spares when foundry finds defects. So that by enabling good SIMD blocks to replace bad ones, they can achieve 1600 SPs, and supply is secured. ATI has been doing this for years now. Nothing spectacular.

 

[jessicafae]

I can not recall any ATI die where there was not a variant with all the shaders enabled.
For example here is RV790 (4890) and it can be seen that the SIMD block has 10x16x5 = 800 shaders (10 rows) so there are not "extra physical shaders that will never be enabled"

I know that lower spec models (4850, 5850, 5830....) will disable parts of chips to help with harvesting, but there was always a part with everything enabled.

 

[jessicafae]

Those extra physical shaders are to help with harvesting. They'll never all be enabled, as the architecture won't permit that. They help serve as spares when foundry finds defects. So that by enabling good SIMD blocks to replace bad ones, they can achieve 1600 SPs, and supply is secured. ATI has been doing this for years now. Nothing spectacular.

hmm. I think you just confirmed that cypress really does have 2560 shaders and that the 1600sp variant (5870) is a harvested part.

 

[btarunr]

hmm. I think you just confirmed that cypress really does have 2560 shaders and that the 1600sp variant (5870) is a harvested part.

That AMD does this is no secret. But that doesn't mean AMD will at some point use these [whatever ZOMG higher number] SPs to make an SKU, or that AMD's design or TSMC's processes have any flaws. RV770 had 960 physical SPs.

 

[jessicafae]

That AMD does this is no secret. But that doesn't mean AMD will at some point use these [whatever ZOMG higher number] SPs to make an SKU, or that AMD's design or TSMC's processes have any flaws. RV770 had 960 physical SPs.

Are you certain RV770 had 12 SIMD units and 960 physical SPs and all 4870s had 160 physical shaders disabled?
Here is a die image of RV770. I count 10 SIMD units (10 rows of 4x4 shaders, just like RV790) meaning no "extra physical shaders which will never be used"

 

[btarunr]

Yes, just as certain that AMD will never use more than 1600 stream processors on the Cypress die.

 

[jessicafae]

ok show me the extra shaders on the RV770 die image.

 

[btarunr]

I don't have to show you anything on the basis of a Picasso art. If you want to learn more about harvesting, refer to this article: http://www.anandtech.com/video/showdoc.aspx?i=3469&p=3

Also I'm inclined to believe that the RV870 die shot is fake. It can't have those many inactive physical SIMD blocks to harvest from.

 

[btarunr]

So 900 stream processors, 100 to harvest.

 

[jessicafae]

http://img.inpai.com.cn/article/2008/12/22/6c889371-b7ac-4863-bab9-a3d1dd01a530.jpg

So 900 stream processors, 100 to harvest.

well you said 960sp and were certain of that. That 9th column is within a SIMD unit (row) and can not be disabled.

 

[btarunr]

well you said 960sp and were certain of that. That 9th column is within a SIMD unit (row) and can not be disabled.

No, it can. The size of an SIMD unit is about the size of that 'number'.

 

[jessicafae]

If you look closely at the die image, that 9th column's structure is different from the other shaders and is most likely the "thread sequencer unit" in the block diagram from this Anandtech
http://www.anandtech.com/video/showdoc.aspx?i=3341&p=3

 

[btarunr]

No, I don't see the difference. Each structure inside the grid looks identical. One of those columns are redundant, used for harvesting.

 

[pantherx12]

BTA stop stating things as if they are 100% fact.

Your not always right, and I'm sure a lot of members here would back me up on that.

I'm not saying Jessicafae is right either.

But your always so set in stone about things that to be frank, you can't be sure about.

ATI and other companies have pulled tricks out they're asses before, until its proven that the die shot is in-fact fake you should stress things as unlikely not "never" and things like that.

Its just arrogant.




*edit*

ATI have been talking about an entire refresh of the 5 series already, maybe the refresh is just activating one extra block etc.

I sincerely doubt their refresh will just be extra ram or clock speed as well.


So such a thing like we're discussing now can be possible.

 

[jessicafae]

From the original image
http://techreport.com/r.x/radeon-hd-4870/die-shot.jpg

I have cut out one SIMD and resized to 300%.
The unit between the Texture units (first two blocks on the left) and 4x4 SPs (on the right) has a different structure to the SPs. You labeled this as 2 extra SPs (9th column) which can be harvested. I think it looks different and is not extra SPs, but most likely the "thread sequencer" or some other controller structure.

 

[Lionheart]

2560 shaders does sound good

 

[cuphe]

From the original image
http://techreport.com/r.x/radeon-hd-4870/die-shot.jpg

I have cut out one SIMD and resized to 300%.
The unit between the Texture units (first two blocks on the left) and 4x4 SPs (on the right) has a different structure to the SPs. You labeled this as 2 extra SPs (9th column) which can be harvested. I think it looks different and is not extra SPs, but most likely the "thread sequencer" or some other controller structure.
http://i827.photobucket.com/albums/zz195/jessica_fae/RV770-die-shot-simd-zoom.jpg

http://i827.photobucket.com/albums/zz195/jessica_fae/anadtech_rv770_SIMDcore_rotate2.png

but with 2560 shaders is quite a big jump from 1600 --> 2560. Other word ur "5890" is almost triple 4870

 

[cadaveca]

The 2560 SP parts were not final revisions. The 2560 SP part also had sideport, but these things were moved in order to improve yields.

The whole 2560 SP thing was something I started many moons ago, as I thought a shader for each pixel line @ 2560x1600, and a 800mhz clock(with 2 pixels per clock per SP), seemed an ideal config.

But, if you read recent interviews, one was with AMD engineering head who stated that even what he wanted was a much bigger chip, than the current Cypress. Ati has it's own mini-fab in Ontario, so they have the capability to run off whatever they like for testing, the shown die-shot is probably one of these test chips.

Running the 4770 chips on the current process for Cypress allowed them to know what error rate they'd have wit hteh process, and it seems to me that they had to go with a much smaller die in order to get closer to target, which still wasn't reached 100%, but they'd have been far worse off(as NV is) had they not had the prior experience making chips @ that process @ TSMC.

 

[Benetanegia]

That die shot is simply fake. Unless Ati suddenly went crazy and at the same time that they were promoting their new strategy of making "slim" chips, they were creating a really big behemoth, much bigger than Fermi. In that die shot not only we see 2560 SPs, we can see 64 identical extructures that can only be ROPs. 2560 SPs and 64 ROPs. Miracles don't happen and you can't squeeze silicon just so much, so such a chip would have nearly 4 billion transistors*. No way.

*Compare the relative size of the SP structures with the chip area on both RV770 and the fake RV870. RV870 is at least 4x bigger. Fake.

 

[cadaveca]

A read for you, Benetanegia:

Even Rick Bergman, a supporter of Carrell’s in the 770 design discussions, agreed that it might make sense to build something a bit more aggressive with 870. It might not be such a bad idea for ATI to pop their heads up every now and then. Surprise NVIDIA with RV670, 770 and then build a huge chip with 870.

http://anandtech.com/video/showdoc.aspx?i=3740&p=3

 

[Benetanegia]

A read for you, Benetanegia:

http://anandtech.com/video/showdoc.aspx?i=3740&p=3

I've read that and I don't remember they mentioned such a chip. In fact, in that article they are saying the planned RV870 was 20-22 mm on a side. I took a ruler. Since RV770 is 16x16 mm the SPs+TMUs take up about 10x10 mm. If we extrapolate that to the RV870 die it gives 36x36 mm (on 55nm node). 36x36 = 1296 mm^2

^^ That on 55nm, but on 40nm what would be? Let's assume linear scaling, 26 mm on a side:

26x26 = 676mm^2

Sorry but it's fake.