Samsung and TSMC Reportedly Struggling with 3 nm Yields

[hs4]

Intel 4 problem isn't yield but cost. Reason for that is that they paid a lot money at ASML for equipment and R&D. They are only making compute tiles at this moment in this node which are about 40 - 60mm² (U/H). So yields are acceptable because tiny chips (tiles) lets see how it works with larger area.

"paid a lot money at ASML for equipment and R&D."

A good strategy to deal with increases in initial/fixed costs is to lengthen the depreciation period. This is the core of the "IDM 2.0" strategy. Their goal is to "Use assets longer." They'll produce Meteor lake tiles there, Sierra Forest and Grinite Rapids, and then they'll either open production capacities in the foundry business or they'll be responsible for Panther lake SoC tiles, and in 2030 they'll produce base tiles.

 

[Proedros]

"paid a lot money at ASML for equipment and R&D."

A good strategy to deal with increases in initial/fixed costs is to lengthen the depreciation period. This is the core of the "IDM 2.0" strategy. Their goal is to "Use assets longer." They'll produce Meteor lake tiles there, Sierra Forest and Grinite Rapids, and then they'll either open production capacities in the foundry business or they'll be responsible for Panther lake SoC tiles, and in 2030 they'll produce base tiles.

View attachment 316388

A good article (IMHO)

Intel says "splitting" fab saves billions of dollars a year, how?

At a recent investor webinar, Intel said that the manufacturing business, including Intel Foundry Services, would report profit and loss/accounting separately. This is said to save Intel billions of dollars a year? We've talked quite a bit about Intel's IDM 2.

www.linkedin.com

Finally it's worth mentioning the issue of yield and capacity as a foundry - this is very different from the past when cutting edge manufacturing processes were all geared towards in-house. TSMC's 7nm and 5nm processes are all said to have gone from 0WPM to 50,000WPM (wafers/month) in just 6 months. Intel's previous history, on the other hand, doesn't look so smooth, with Ice Lake and Sapphaire Rapids having slow ramp-ups.

IDM 2.0 does seem to us to be the key to Intel's "return to the throne" in the medium to long term, and it doesn't matter that Meteor Lake and Sapphaire Rapids won't break the mould, because they are all products that are preparing the ground for the next generation of technology. The next generation of technology is ready to take the lead.

 

[las]

Intel 4 this year, Intel 20A next year, let the competition begin

 

[hs4]

A good article (IMHO)

Intel says "splitting" fab saves billions of dollars a year, how?

At a recent investor webinar, Intel said that the manufacturing business, including Intel Foundry Services, would report profit and loss/accounting separately. This is said to save Intel billions of dollars a year? We've talked quite a bit about Intel's IDM 2.

www.linkedin.com

They figured out another way for using assets longer in the last days of IDM 1.0. They planned to make two generations of progress at once and use them for twice as long. This is why Intel 10nm (now Intel 7) has the same physical geometry as TSMC N7. However, it is well known that this has led to many eggs (innovations) being put in one basket, resulting in significant delays and damage.

IDM 2.0 was advertised immediately after Gelsinger became CEO, but I think the impact on investment in has been little understood until now.

Sapphire Rapids also tried to introduce many new features at once (by the way, all SPR tiles are manufactured on Intel 7, not planned for IDM 2.0), and also it severely delayed. In January of this year, the NYT reported on a situation in which too many new features of the SPR had spawned 12 iterations of stepping.

Intel 4 this year, Intel 20A next year, let the competition begin

Only one fab for Intel 4 volume ramp has been built, Fab 34 in Ireland, thus Intel 4 and 20A will not compete with each other. However, this results in the loss of capacity to produce MTL-S for desktops.

The results of Intel 4 development will be used when Intel 7 is converted to base tiles, etc. Incidentally, they are offering foundry services for an improved version of the 22nm with cost-effective layers adopted from 14nm.

 

[qcmadness]

You can buy TSMC 3nm product (iPhone 15 Pro / Pro Max) now.

Intel is going to ramp up Intel 3 late next year.

Intel is lacking volume severely. We don't know if Intel 3 is superior than TSMC N3. But in terms of volume, TSMC is in a much better shape than Intel.

 

[Denver]

Intel 3 isn't "3nm", Just like the soon to be released MTL Intel 4 are not "4nm". It's an optimized "7nm" that going to be comparable to TSMC 3nm. The current Intel 10nm is called intel 7 because it's equivalent to TSMC 7nm.
Nodes names are a marketing name everywhere, ever since fabs engineers figured out that at some point simply making things smaller would bring a bunch of issues. TSMC 3nm isn't actually 3nm, but is as performant as a real 3nm would be in theory. Intel choose to use a "TSMC rating system" to avoid people thinking that their nodes are inferior because the number is bigger.

By whatever parameter you choose, Intel's processes are inferior to TSMC's. Intel 4 will not even reach the first generation 5nm density. lol

intel 7(based on 13900k)-> 100.78mTr/mm²
Intel 4 -> 123.4mTr/mm²
TSMC 5nm -> 138
TSMC 4nm -> 143
TSMC 3nm (A17 pro)-> 183

 

[Proedros]

Don't forget Intel is using (and) TSMC to bring the CPU to market.

Intel Meteor Lake Tile/Chiplet Manufacturer / Node
CPU Tile Intel / 'Intel 4'
3D Foveros Base Die Intel / 22FFL (Intel 16)
GPU Tile (tGPU) TSMC / N5 (5nm)
SoC Tile TSMC / N6 (6nm)
IOE Tile TSMC / N6 (6nm)

 

[alawadhi3000]

By whatever parameter you choose, Intel's processes are inferior to TSMC's. Intel 4 will not even reach the first generation 5nm density. lol

intel 7(based on 13900k)-> 100.78mTr/mm²
Intel 4 -> 123.4mTr/mm²
TSMC 5nm -> 138
TSMC 4nm -> 143
TSMC 3nm (A17 pro)-> 183

You are comparing apples to oranges, the Intel 4 density is using the high performance library whereas your provided values for Intel 7 and all the TSMC processes are with high density library.
Intel 4 with high density library can be ~200 MTr/mm2.

 

[qcmadness]

You are comparing apples to oranges, the Intel 4 density is using the high performance library whereas your provided values for Intel 7 and all the TSMC processes are with high density library.
Intel 4 with high density library can be ~200 MTr/mm2.

It does not matter as the density of real products are far lower than that.

 

[hs4]

Don't forget Intel is using (and) TSMC to bring the CPU to market.

Intel Meteor Lake Tile/Chiplet Manufacturer / Node
CPU Tile Intel / 'Intel 4'
3D Foveros Base Die Intel / 22FFL (Intel 16)
GPU Tile (tGPU) TSMC / N5 (5nm)
SoC Tile TSMC / N6 (6nm)
IOE Tile TSMC / N6 (6nm)

Zen4c is logically the same as Zen4, which means it has the same number of transistors, but by using high-density cells instead of high-performance cells, it succeeded in reducing the area by 2/3, or in other words, increasing the density by 1.5 times. . In exchange, the maximum clock has been lowered to 3.5 GHz. The number you gave for the density of N5 is the density if only high-density cells were used i.e. can only make Zen4c with a low maximum clock.

You are comparing apples to oranges, the Intel 4 density is using the high performance library whereas your provided values for Intel 7 and all the TSMC processes are with high density library.
Intel 4 with high density library can be ~200 MTr/mm2.

Intel 4 is effectively a process dedicated to Compute tile and does not include high-density cells in its library. High density cells (probably 2/2 fins) will be provided by Intel 3.

 

[Proedros]

Zen4c is logically the same as Zen4, which means it has the same number of transistors, but by using high-density cells instead of high-performance cells, it succeeded in reducing the area by 2/3, or in other words, increasing the density by 1.5 times. . In exchange, the maximum clock has been lowered to 3.5 GHz. The number you gave for the density of N5 is the density if only high-density cells were used i.e. can only make Zen4c with a low maximum clock.


Intel 4 is effectively a process dedicated to Compute tile and does not include high-density cells in its library. High density cells (probably 2/2 fins) will be provided by Intel 3.

Just pointing out that until now Intel needs TSMC to bring its CPU in the market.

 

[hs4]

Just pointing out that until now Intel needs TSMC to bring its CPU in the market.

Counting backwards from the CPU ID, designing of Meteor lake started before it of Raptor lake. In other words, it had been started before Tiger lake H35. That time it was unclear whether 10nm could achieve a decent yield, and there was a risk of abandonment of Fab. As you can see from the Nov. 6. 2020 library of Moore's law is dead, the originally planned Ocean Cove had been abandoned and it was switched to the Redwood Cove, redesigned Golden Cove manufacturable in TSMC.

Currently, the situation has changed significantly, and Intel's process development seems to be progressing relatively smoothly. On the other hand, TSMC appears to have encountered the same interconnect layer issues with 3nm generation that Intel also encountered with their 10nm generation.

@Proedros
P.S. I seem to have replied to the wrong post. I meant to reply to the post below.

By whatever parameter you choose, Intel's processes are inferior to TSMC's. Intel 4 will not even reach the first generation 5nm density. lol

intel 7(based on 13900k)-> 100.78mTr/mm²
Intel 4 -> 123.4mTr/mm²
TSMC 5nm -> 138
TSMC 4nm -> 143
TSMC 3nm (A17 pro)-> 183

 

[alawadhi3000]

It does not matter as the density of real products are far lower than that.

It does matter.

Intel 4 is effectively a process dedicated to Compute tile and does not include high-density cells in its library. High density cells (probably 2/2 fins) will be provided by Intel 3.

I was responding to the flawed comparison and the theoretical density that can be provided by the process, not their decision on what library they offer with the process.

 

[Denver]

It does matter.


I was responding to the flawed comparison and the theoretical density that can be provided by the process, not their decision on what library they offer with the process.

Yeah... It's hard to know, chips with a lot of cache and designed to run at high clocks won't reach the density mentioned there. Mobile chips like the 7840U, however, are within that ideal density.

 

[PapaTaipei]

And does anyone in the public knows the real size of those "3nm" nodes?

 

[qcmadness]

And does anyone in the public knows the real size of those "3nm" nodes?

We will not know for sure until we get the actual products, which is slated to be in 2025.

 

[AnotherReader]

And does anyone in the public knows the real size of those "3nm" nodes?

TSMC has shared numbers for the relevant dimensions. As you can see, 3 nm is just a marketing name, but since TSMC's customers are silicon design houses, it doesn't matter. The customers know the exact characteristics of the process.

 

[TechHalp]

All to keep prices high on their existing nodes

Smaller nodes are more profitable for the company, DUH

 

[bonehead123]

"Samsung and TSMC Reportedly Struggling with 3 nm Yields"

But of course they are.... how else will they be able to justify the upcoming price hikes that are sure to come with these new chips.

 

[AnotherReader]

Smaller nodes are more profitable for the company, DUH

No, longer lived nodes are more profitable for the company as R&D is amortized over years or even decades. Look at 28 nm; it was introduced by TSMC in late 2011 and with the termination of the unlamented 20 nm node, it's the best non-Finfet TSMC node. Even in 2023 Q2, it accounted for 11% of revenue. Unlike N3, there isn't significant investment required to realize that revenue.

 

[TechHalp]

Figure from Techinsight


2) Intel 7 can consume a large amount of power simply because it has a higher maximum clock. If Raptor lake is clock-limited to the same clock/same benchmark score as the Ryzen 5000 series (N7), it will consume less power than the subject of comparison.
The Ryzen 7000 series (N5) is not much different in power efficiency from Raptor lake as a result of increasing the maximum clock, and the 7800X3D is more efficient due to lower clock due to lack of heat dissipation capability by the V-Cache.
View attachment 316385

This 'logic' is abysmal. Intel only uses more power because the clock is higher, yea and trucks only use more gas because they have 8 cylinders. Dumb argument. Completely ignoring the laws of physics. AMD's nodes have increased efficiency, period. No debate at all.

Get this uneducated crap out of here. Weak attempt.

 

[AnotherReader]

"Samsung and TSMC Reportedly Struggling with 3 nm Yields"

But of course they are.... how else will they be able to justify the upcoming price hikes that are sure to come with these new chips.

Apple is only paying TSMC for working dies so this isn't working out well for TSMC so far.

 

[TechHalp]

No, longer lived nodes are more profitable for the company as R&D is amortized over years or even decades. Look at 28 nm; it was introduced by TSMC in late 2011 and with the termination of the unlamented 20 nm node, it's the best non-Finfet TSMC node. Even in 2023 Q2, it accounted for 11% of revenue. Unlike N3, there isn't significant investment required to realize that revenue.

View attachment 316450

Yea if you have no foresight that looks pretty good, until your chip is the slowest, least efficient one that exists and your stock goes down 20% in 5 years. What's 11% of nothing again?

 

[AnotherReader]

Yea if you have no foresight that looks pretty good, until your chip is the slowest, least efficient one that exists and your stock goes down 20% in 5 years. What's 11% of nothing again?

You claimed that new nodes are the most profitable. I pointed out that they require significant investment and older nodes are actually the really profitable ones. Of course, if you want more customers, you need to stay at the leading edge. However, there's a big world outside smartphones and PCs that doesn't need the latest node. If your design is pad limited or doesn't require high performance, older nodes are just fine.

 

[TechHalp]

You claimed that new nodes are the most profitable. I pointed out that they require significant investment and older nodes are actually the really profitable ones. Of course, if you want more customers, you need to stay at the leading edge. However, there's a big world outside smartphones and PCs that doesn't need the latest node. If your design is pad limited or doesn't require high performance, older nodes are just fine.

Your whole argument is that we should still be on 3000 nm because it would definitely be cheaper to make. Got it. Never innovate, never change, never improve, that's how to stay competitive. I've often said intel was a successful company when they completely stopped innovating.

Not like you could shrink nodes or use chiplets and over time they would outweigh the profit of older architectures. Of course not that would be ridiculous. Must be why cell phones that used to cost $500 can be bought at 711 for 20 bucks.

You can make excuses and arguments and spend your entire pay check on Intel every week, and it wouldn't make a difference. Because where the money actually is in the server market, they are inferior and nowhere to be seen. Too few cores because of their architecture, too little efficiency because of bad design. Period, full stop, stock price reflects it perfect.