Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture

[PapaTaipei]

Didn't a renowned Intel engineer said that after 28nm the transistor density increase on paper but electricity leaks make it so that more and more of the transistors have to be disabled, some wild figures like more than 50% on the 10nm nodes...

 

[ARF]

Theoretical densities at best ! As it has been demonstrated effective densities are far lower compared to theoretical densities and the gap between those two increases on each generation : The TRUTH of TSMC 5nm .

Also something to keep in mind is GAA offers more advantages than simple increase in denistiy compared to FinFet ( reduced leaking / higher frequency etc ) .

The listed in Wiki maximum densities are for the SRAM cells. transistors - How dense is SRAM compared to random logic? - Electrical Engineering Stack Exchange

 

[eazen]

These are TSMC '7nm' equivalents at best, you have to understand that the current nanometer numbers make no sense whatsoever anymore, and Samsung is not cheating one step lower, but multiple.

Their 8nm is on par with TSMC 14~12nm go figure. The gap is so huge it makes no sense whatsoever. I don't trust a single statement coming from Samsung wrt technological parity.

Samsung is about 1 node behind, not 2. 8nm was more or less comparable to TSMC 7N, you can see it in the density data in TPUs database, 6900 XT vs 3090 for example.

Look at the information: 3 nm process - Wikipedia
Samsung's 3GAE should be like TSMC N4 process.
TSMC N4 - 196.6 MTra / sq. mm.
Samsung 3GAE - 202.85 MTra / sq. mm.
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5 nm process - Wikipedia

Thanks for proving me right and contradicting yourself then? And I don’t know what you were laughing at, maybe at yourself. I clearly said 3-4, now you’re saying it will be like 4, thanks for making it easy for me to counter you. Lol

 

[MxPhenom 216]

"reduce area by 16% compared to 5 nm"

Wow that's ridiculous low, definitely more a 5nm+ than a 3nm.

That isn't that low. Especially for first generation of a new FET technology at node sizes of diminishing returns. Its almost impossible to make a transistor work at these sizes with a Finfet. Not enough control of the channel.

Going from a planar FET to a Fin made manufacturing and design of ICs way way more complicated. Basically, went from a few hundred design rules to several thousands. GAAFETs will make that even more complicated.

Didn't a renowned Intel engineer said that after 28nm the transistor density increase on paper but electricity leaks make it so that more and more of the transistors have to be disabled, some wild figures like more than 50% on the 10nm nodes...

This is pretty true. Though I wonder if that Engineer had new FET designs in mind that have since come out to get us under 22-28nm. One of the biggest problems VLSI engineers have to overcome with the never-ending demand for high performing ICs and thus the never-ending reduction is node sizes is the fact that controlling the flow of elections across the channel is harder as you get smaller. Electrons have a tendency to flow across the channel even if the transistor is off (Leakage). And then you have certain higher speed designed FETs that almost never turn off due to how quickly they are switching (Frequency) which also contributes to leakage power. That is why the Finfet even came out was to be able to control that behavior better with the channel being 3d and in contact with the gate from 3 sides rather than 1 (planar). Leakage dropped significantly when Finfet came.

 

[ARF]

Thanks for proving me right and contradicting yourself then? And I don’t know what you were laughing at, maybe at yourself. I clearly said 3-4, now you’re saying it will be like 4, thanks for making it easy for me to counter you. Lol

It is 3 or 4 (very different), maybe 5?

 

[eazen]

It is 3 or 4 (very different), maybe 5?

We are all speculating.. My estimation is just a estimation and most likely correct.

 

[MxPhenom 216]

Another thing everyone needs to realize is that a long time ago the nm rating of a node actually meant exactly what it says. That is usually denoting the length of the channel of the FET. This is something that cannot be changed for cells in a node, but you can alter its width which contributes to driving strength/throughput of the FET. A 45nm FET meant the length of the channel is 45nm long. Now-a-days its mostly used as marketing by chip makers and semiconductor foundries. More often than not the FET dont actually have that length of a channel now. The fastest FETs in the nodes library of cells get close to it however. These FETs are also mostly reserved for paths that require faster fets in a chips design, but these also carry higher leakage, so usually engineers and tools being used restrict these FETs from being used to much.

 

[ARF]

We are all speculating, maybe stop being a jerk. My estimation is just a estimation and most likely correct.

Claiming "3-4" is like claiming any colour from white to black. It is a wide guesstimate without any effort to give a correct reply.

 

[the54thvoid]

You're both like kids and the thread doesn't need your drama. Take a break gentle people.

 

[ThrashZone]

Hi,
870 series does pretty much suck
But it's the first that I know of.

980 first firmware was crap