Samsung Electronics Launches Enhanced 1TB microSD Cards

[Vincero]

I get that, but wouldn't the heat these generate be significantly reduced by using a more modern manufacturing process? Not to mention you increase the number of dies on a wafer. I understand these don't require the n3 process...

Not necessarily - smaller processes don't always yield additional efficiency - the smaller the transistor elements generally the higher the leakage curent between/through the FET gate (which is why even with smaller processes, the actual transistor size is much bigger - TSMC's / Samsung / Intel 12nm down to 3nm isn't the actual size of the transistors in the chip.

For something like a NAND array this would be quite an issue, especially as it was until recently acknowledged that ~15nm was the limit at which you can fab NAND storage devices reliably. Even at 28nm the transistors will be bigger than that size, but other increased material thicknesses for chip features will bring lower circuit resistance, etc.