Samsung's 2 nm GAA Node Process Test Yields Reportedly Pass 40% Mark

[T0@st]

According to the latest South Korean semiconductor industry whispers, Samsung's 2 nm GAA node process (aka SF2) development team has hit another pleasing experimental production milestone. An Asia Economy SK news article has sourced insights from inside track players—one unnamed mole posited that: "the 2 nm yield currently under development at Samsung Foundry is much better than previously known...and more positive than the (reportedly abandoned) 3 nm process." A combination of relatively new leadership and a rumored welcoming of first wave High-NA EUV equipment has likely bolstered next-gen efforts, after late 2024's alleged failure of 3 nm prototypes. Leaks from earlier in 2025 indicated SF2 test yields wavering around 20-30%; far from ideal—back then, insider reports suggested that TSMC was well on the way to achieving 60% rates with a competing 2 nm product line. Asia Economy has picked up on mutterings about Samsung's current progress—latest outputs: "have exceeded 40% in the wafer testing stage at a post-processing company."

Industry watchdogs reckon that the South Korean's foundry business is making good progress; perhaps on track to commence speculated mass production by the third quarter of this year—just in time to get finalized flagship "Exynos 2600" mobile chips in the manufacturing pipeline. The Taiwanese rumor mill indicated a major milestone "completion" of TSMC's 2 nm trial phase at some point last month—insiders mentioned excellent yield rates: in the region of 70-80%. Cross-facility mass production could start later this year, but experts propose that the market leader will be implementing price hikes. These "elevated charges" could send loyal TSMC customers in the direction of an alternate source of 2 nm wafers: Samsung. Fresh semicon biz gossip has the likes of Apple, AMD and NVIDIA in the picture.



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[Wirko]

That sounds good, unless yield percentages are expressed in some fantasy units in the same way as fantasy nanometres are.

 

[GenericUsername2001]

Aren't yield rates without knowing the die size pointless? I mean 40% yields on big 600 mm2 chip would be good, but 40% yields on a 60 mm2 chip would be pretty bad.

 

[TheLostSwede]

Aren't yield rates without knowing the die size pointless? I mean 40% yields on big 600 mm2 chip would be good, but 40% yields on a 60 mm2 chip would be pretty bad.

This is a few years old, but explains how node testing is done.

Test Chips Play Larger Role At Advanced Nodes

Opinions diverge about whether to use fewer test chips, or whether to put more diagnostics into those chips.

semiengineering.com

 

[Denver]

This is a few years old, but explains how node testing is done.

Test Chips Play Larger Role At Advanced Nodes

Opinions diverge about whether to use fewer test chips, or whether to put more diagnostics into those chips.

semiengineering.com

I thought Samsung typically used its High-end Exynos chips by default as test chips to measure yields. TSMC should also be using a similarly sized 100–140mm² ARM chip to report their yields, right?

 

[freeagent]

I thought Aliens were helping us out, what gives?

 

[Athena]

This is a few years old, but explains how node testing is done.

Test Chips Play Larger Role At Advanced Nodes

Opinions diverge about whether to use fewer test chips, or whether to put more diagnostics into those chips.

semiengineering.com

This is also a interesting read if people are really curious... https://en.wikipedia.org/wiki/Semiconductor_device_fabrication#Wafer_test it covers lots of things