SK Hynix Shifts to 3nm Process for Its HBM4 Base Die in 2025

[Nomad76]

SK Hynix plans to produce its 6th generation high-bandwidth memory chips (HBM4) using TSMC's 3 nm process, a change from initial plans to use the 5 nm technology. The Korea Economic Daily reports that these chips will be delivered to NVIDIA in the second half of 2025. NVIDIA's GPU products are currently based on 4 nm HBM chips. The HBM4 prototype chip launched in March by SK Hynix features vertical stacking on a 3 nm die., compared to a 5 nm base die, the new 3 nm-based HBM chip is expected to offer a 20-30% performance improvement. However, SK Hynix's general-purpose HBM4 and HBM4E chips will continue to use the 12 nm process in collaboration with TSMC.

While SK Hynix's fifth-generation HBM3E chips used its own base die technology, the company has chosen TSMC's 3 nm technology for HBM4. This decision is anticipated to significantly widen the performance gap with competitor Samsung Electronics, which plans to manufacture its HBM4 chips using the 4 nm process. SK hynix is currently leading the global HBM market with almost 50% of market share, most of its HBM products been delivered to NVIDIA.



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[AnotherReader]

The headline should be reworded to make it clear that it applies to the base die. TSMC's processes, just like most logic oriented fabs, are ill suited to DRAM.

 

[Nomad76]

The headline should be reworded to make it clear that it applies to the base die. TSMC's processes, just like most logic oriented fabs, are ill suited to DRAM.

Right, thanks

 

[AnotherReader]

Right, thanks

Thanks for the quick correction. This is a big part of what makes TPU great.

 

[Wirko]

Who does the TSV stacking? I assume every HBM maker does it for their own stacks but I don't know. The 21st century sure isn't known for simple supply chains.

 

[AnotherReader]

Who does the TSV stacking? I assume every HBM maker does it for their own stacks but I don't know. The 21st century sure isn't known for simple supply chains.

That's a good question. Given that the HBM makers also make other products that use TSVs, e.g. NAND and LRDIMMs for high memory capacity servers, I would wager they do it themselves. @TheLostSwede Do you have any insights?

 

[Wirko]

That's a good question. Given that the HBM makers also make other products that use TSVs, e.g. NAND and LRDIMMs for high memory capacity servers, I would wager they do it themselves.

They use good old wire bonding for NAND, probably because it's good enough for current data rates (around 3200 MT/s) and widely available too.

 

[AnotherReader]

They use good old wire bonding for NAND, probably because it's good enough for current data rates (around 3200 MT/s) and widely available too.

Until HBM3, those data rates would have been sufficient for HBM as well.