WRITE OPERATIONS
Byte Write
In Byte Write mode the Master sends a START, followed by Slave address, byte address and data to be written
(Figure 5). The Slave acknowledges all 3 bytes, and the Master then follows up with a STOP, which in turn starts the internal Write operation (Figure 6). During internal Write, the Slave will not acknowledge any Read or Write request from the Master.
Page Write
The CAT34C02 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. A page is selected by the
4 most significant bits of the address byte following the Slave address, while the 4 least significant bits point to the byte within the page. Up to 16 bytes can be written in one Write cycle (Figure 7).
The internal byte address counter is automatically in- cremented after each data byte is loaded. If the Master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a ‘wrap-around’ fashion
(within the selected page). The internal Write cycle starts immediately following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the CAT34C02 is busy writing or is ready to accept com- mands. Polling is implemented by interrogating the device with a ‘Selective Read’ command (see READ OPERATIONS).
The CAT34C02 will not acknowledge the Slave address, as long as internal Write is in progress.
Hardware Write Protection
With the WP pin held HIGH, the entire memory, as well as the SWP flags are protected against Write operations
(Figure 8). If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT34C02.
SOFTWARE WRITE PROTECTION
The lower half of memory (first 128 bytes) can be pro- tected against Write operations by setting one of two Software Write Protection (SWP) flags.
The Permanent Software Write Protection (PSWP) flag can be set, but not cleared, by the user. This flag can be set or queried ‘in-system’.
The Reversible Software Write Protection (RSWP) flag can be set or queried and cleared by the user during DDR2 DIMM testing. All RSWP related commands require the presence of a very high voltage - VHV - on address pin A0 and fixed CMOS logic levels on the other two address pins. Thus, for RSWP related commands, the address pins are used to decode the mode, rather than to ‘identify’ the device.
A detailed description of all SWP commands can be found in Table 1. All these commands are preceded by
a START and terminated with a STOP, following the ACK
or NoACK from the CAT34C02.
The first four bits of the Slave address byte must be
0110, in contrast to the regular 1010 ‘preamble’ used for memory Read or Write commands. The next three bits must match the logic state of the three physical address pins. For PSWP commands, the address pins are all at CMOS levels, and any one of the eight possible combinations is valid. For RSWP commands, the A0 pin must be at VHV and will be interpreted as a logic ‘1’. The other two address pins must be at fixed CMOS levels, A2 at GND and A1 at GND for Set RSWP commands and at VCC for Clear RSWP commands. The VHV level must be established on pin A0 before the START and maintained just beyond the STOP.
Commands where the last bit of the Slave address is
‘0’, are similar to a ‘Byte Write’, except that both byte address and data following the Slave address, are ‘don’t care’ (i.e. just place holders) (Figure 12).
Query type commands, where the last bit in the Slave address is ‘1’, are somewhat similar to an’‘Immediate Address Read’, except that no data byte is expected from the device; the ACK or NoACK itself is the response to the query. Therefore, the Master will immediately follow up this response with a STOP (Figure 13).
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