TPU's Core i7 Overclocking and Feedback

[mojom@n]

Hows this one?

 

[Fitseries3]

almost 90k and sub 6sec...

 

[Solaris17]

That's sounds more like chi'ing it to work. lol.

its called the will and the word belgarath

 

[Fitseries3]

beat you by a hair...

and for cpu speed.....

 

[Solaris17]

lol a fight

 

[Fitseries3]

 

[Solaris17]

very good grats fit you still need to build me a phase.

 

[DaMulta]

who wants to help me out here?

this is what all auto gives me for 4ghz....

4ghz auto
cpu = 1.42
qpi = 1.363
pll = 1.812
dram = 1.56
ioh i_h = 1.508
ioh = 1.131
ich i_s = 1.508
ich = 1.111

i bumped the cpu to 1.45v and retesting but damn this thing is being a total PITA

EDIT: dammit.... it froze loading cpu test 1

QPI

The Intel QuickPath Interconnect ("QuickPath", "QPI")[1][2][3] is a point-to-point processor interconnect developed by Intel to compete with HyperTransport. Prior to the announcement of the name, Intel referred to it as Common System Interface or "CSI". It will replace the Front Side Bus (FSB) for Desktop, Xeon, and Itanium platforms. Intel will first deliver it in November 2008 on the Intel Core i7 desktop processor and the X58 chipset, and it will be used on new Nehalem-based Xeon processors[4] and Tukwila-based Itanium processors.[5]

The QPI is an element of a system architecture that Intel calls the QuickPath architecture that implements what Intel calls QuickPath technology.[6] In its simplest form on a single-processor motherboard, a single QPI is used to connect the processor to the IO Hub (e.g., to connect a Core i7 to an X58.) In more complex instances of the architecture, separate QPI links connect one or more processors and one or more IO hubs or routing hubs in a network on the motherboard, allowing all of the components to access other components via the network. As with AMD's Hypertransport, the QuickPath Architecture assumes that the processors will have integrated memory controllers, so a multiprocessor system implements a NUMA architecture.

Each QPI comprises two 20-bit point-to-point links, one in each direction, with a separate clock in each direction, for a total of 42 signals. Each signal is a differential pair, so the total number of pins is 84.

Performance numbers for QuickPath are reported to be 4.8 to 6.4 Gigatransfers per second (GT/s) per direction. Therefore the bandwidth amounts to 12.0 to 16.0 GB/s per direction, or 24.0 to 32.0 GB/s per link.[7]

On high-reliability servers, A QPI link can operate in a degraded mode. If one or more of the 20+1 signals fails, the interface will operate using 15+1, 10+1, or even 5+1 remaining signals, even reassigning the clock to a data signal if the clock fails.

The initial Nehalem implementation uses a 20-bit wide 25.6 GB/s link (as reported in the Intel Nehalem Speech on IDF). This 25.6 GB/s link provides exactly double the theoretical bandwidth of Intel's 1600 MHz FSB used in the X48 chipset.

pll

A phase-locked loop or phase lock loop (PLL) is a control system that generates a signal that has a fixed relation to the phase of a "reference" signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. A phase-locked loop is an example of a control system using negative feedback.

In simpler terms, a PLL compares the frequencies of two signals and produces an error signal which is proportional to the difference between the input frequencies. The error signal is then low-pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the frequency in the opposite direction so as to reduce the error. Thus the output is locked to the frequency at the other input. This input is called the reference and is often derived from a crystal oscillator, which is very stable in frequency.

Typically, the reference clock enters the chip and drives a phase locked loop (PLL), which then drives the system's clock distribution. The clock distribution is usually balanced so that the clock arrives at every endpoint simultaneously. One of those endpoints is the PLL's feedback input. The function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched. From a control theory perspective, the PLL is a special case of the Kalman filter.

PLLs are ubiquitous -- they tune clocks in systems several feet across, as well as clocks in small portions of individual chips. Sometimes the reference clock may not actually be a pure clock at all, but rather a data stream with enough transitions that the PLL is able to recover a regular clock from that stream. Sometimes the reference clock is the same frequency as the clock driven through the clock distribution, other times the distributed clock may be some rational multiple of the reference.

Elements

[edit] Phase detector

The two inputs of the phase detector (PD) are the reference input and the feedback from the voltage controlled oscillator (VCO). The PD output controls the VCO such that the phase difference between the two inputs is held constant, making it a negative feedback system.

There are several types of phase detectors in two main categories of analog and digital.

[edit] Analog

The analog phase detector takes the form of an ideal frequency mixer. This device produces an output that is the product of the two instantaneous input voltages. The multiplication process produces the classical sum and difference frequencies of mixers, but when used as a phase detector, a Low-pass filter is required to attenuate the sum frequency. When the remaining difference frequency is low enough to pass through the filter with sufficient amplitude, it moves the VCO frequency closer to the reference frequency allowing the loop, after a transient period, to acquire lock. This process is called "capture" and the maximum frequency separation (between reference input and VCO) that allows lock is the "capture range". The loop is called "locked" when the VCO is on the same frequency as the reference and differs only in some amount of phase.

When the loop is locked, the sum and difference are still present, but the sum becomes a frequency twice that of the reference. The difference, which appears as the average value of the sum frequency, becomes, after the filter, a DC component proportional to the (cosine of the) phase difference. This then sets the VCO frequency.

The phase difference at the inputs, when in lock, is near 90 degrees for this type; the exact amount being determined by the loop gain. Though an additional integration can be added to bring it to 90, this is rarely required in simple loops.

The phase and amplitude characteristics of the low-pass filter are dominant factors in determining the capture range, lock time and transient performance of the loop.

Two common implementations are the double balanced diode mixer and the four-quadrant multiplier (which is also a double balanced mixer).

The presence of the sum frequency at the mixer output also adds complexity in applications where spectral purity of the VCO signal is important. This causes frequency modulation of the VCO at twice the reference frequency. The resulting unwanted (spurious) sidebands, also called "reference spurs" can dominate the filter requirements and reduce the capture range and lock time well below the requirements. In these applications the more complex digital phase detectors are used which do not have as severe a reference spur component on their output.

[edit] Digital

The simplest is a XOR gate. It compares well to the analog mixer in that it locks near a 90° phase difference and has a square-wave output at twice the reference frequency. The average value of this square wave is the DC component that sets the VCO frequency. The square-wave changes duty-cycle in proportion to the phase difference resulting, after the filter, in the VCO control voltage. It requires inputs that are symmetrical square waves, or nearly so. The remainder of its characteristics are very similar to the analog mixer for capture range, lock time, reference spurious and low-pass filter requirements.

A more complex digital PD uses a simple state machine to determine which of the two signals has a zero-crossing earlier or more often. This brings the PLL into lock even when it is off frequency and is known as a Phase Frequency Detector.

A PLL with a bang-bang charge pump phase detector supplies current pulses with fixed total charge, either positive or negative, to the capacitor acting as an integrator. A phase detector for a bang-bang charge pump must always have a dead band where the phases of the reference and feedback clocks are close enough that the detector fires either both or neither of the charge pumps, for no total effect. Bang-bang phase detectors are simple, but are associated with significant minimum peak-to-peak jitter, because once in lock the phase offset drifts inside the two extreme values of the dead band without triggering any corrections.

A proportional phase detector employs a charge pump that supplies charge amounts in proportion to the phase error detected. Some have dead bands and some do not. A dead band is an area where small changes in phase difference produce no correction to the VCO. Specifically, some designs produce both "up" and "down" control pulses even when the phase difference is zero. These pulses are small, nominally the same duration, and cause the charge pump to produce equal-charge positive and negative current pulses when the phase is perfectly matched. If the inputs are slightly mismatched, either the up or down pulse will contain slightly more charge than the other and the PLL will be able to correct the offset. PLLs with this kind of control system don't exhibit a dead band and typically have lower minimum peak-to-peak jitter that is determined by other limiting factors.

These types, having outputs consisting of very narrow pulses at lock, are very useful for applications requiring very low VCO spurious outputs. The narrow pulses contain very little energy and are easy to filter out of the VCO control voltage. This results in low VCO control line ripple and therefore low FM sidebands on the VCO.

It is frequently required to know when the loop is out of lock. The more complex digital phase-frequency detectors usually have an output that allows a reliable indication of an out of lock condition.

dram

Dynamic random access memory

DX58SO motherboard platform consists of the Intel Core i7 processor (CPU), Intel X58 Express Chipset (IOH) and the ICH. The CPU now incorporates the system memory controller and accesses DDR3 memory through three independent memory channels. The IOH provides support for the two PCIe graphics slots and connects to the CPU via the Quick Path Interconnect (QPI) bus. The ICH provides the support for the SATA, USB and other system interfaces and is connected to the IOH via the DMI bus.

IOH

The IOH provides support for the two PCIe graphics slots and connects to the CPU via the Quick Path Interconnect (QPI) bus.

ICH

ICH provides the support for the SATA, USB and other system interfaces and is connected to the IOH via the DMI bus.

Measurable voltages are: DRAM; ICH_PCIE; ICH; IOH_PCIE; IOH; QPI/DRAM; CPU_PLL, and CPU vCore.

ioh i_h could just be the ioh chipset itself

ich i_s same goes for this one

 

[mojom@n]

beat you by a hair...

Hows this then at same 4205mhz.

 

[Fitseries3]

disabled HT?

 

[mojom@n]

disabled HT?

I always have it disabled as when i overclock i loose the extra multi(turbo Boost). also i have no programs that would take use of 8 threads. You will notice the other test is multi threading is disabled as well.

 

[Fitseries3]

 

[DaMulta]

pi lol

I only stress CPU hard test

I always lol when I see someone running pi
----

U like?

http://www.newegg.com/Product/Product.aspx?Item=N82E16813130215

fing sweet

TW3X4G1600C9DHX 12GB KIT 3X4GB DDR3 1600MHZ 2X240DIMM UNBUFF 9-9-9-24
In Stock : YES

Our Price:
$275.80
and another set
24GB

 

[Tatty_Two]

I think the real strength of this chip, coupled with the memory bandwidth etc would really show in Sceincemark 2 which tests number crunching and funnily enough memory latency and bandwidth..............maybe we should resurrect that thread which I am subscribed to and have not seen active for ages.

 

[InnocentCriminal]

Fits, Dark - don't know if you have this or not but I thought you'd like to know.

X58 i7 8.11 hotfix.

Hope it helps!

 

[Fitseries3]

Fits, Dark - don't know if you have this or not but I thought you'd like to know.

X58 i7 8.11 hotfix.

Hope it helps!

is there notes on what it fixes?

8.11 is total trash on this setup. im just curios as to what has been fixed.

 

[DaMulta]

one game lol(IDRK)

These is a release note somewhere.....

 

[Fitseries3]

yeah i see em.

1st test in vantage i get 5-10fsp and the screen is all white. total crap.

if i use 8.10 i get 40-1XX no problem and everything looks fine.

 

[InnocentCriminal]

That's a shame, was hoping that would have increased something for you. Would have been more fun for us all.

 

[DaMulta]

Fit you have advanced Ai turned on correct?

That's where the hot fixes come in. The drivers take over the program, and fix their bad coding. Not ATi bad coding.

Just wondering, but I think you already know this.

 

[Fitseries3]

2.98ghz...

dual x2 at stock...

 

[HTC]

2.98ghz...

dual x2 at stock...

That's better then this one @ a very slightly higher clock with the x2 also @ stock:

 

[Fitseries3]

oh shit.... thats odd. almost the same score with 1 card and 2 cards. wtf is up with that?

 

[Fitseries3]

is it the same on vantage....

 

[Solaris17]

lower cpu clock? if so its probably bottlnecking bring her upto 4Ghz