JEDEC is Preparing New Raw Card DIMM Designs with DDR5 Clock Drivers for Improved Performance and Stability at 6400 Mbps and Beyond
JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced upcoming raw card designs currently in development in JEDEC's JC-45 Committee for DRAM Modules in collaboration with the JC-40 and JC-42 Committees. These raw card memory device standards are intended for use in client computing applications such as laptops and desktops and will be supported by related appendix specifications. The forthcoming raw cards will also complement two DDR5 Clock Driver standards published earlier this year: JESD323: DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification and JESD324: DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification.
Integrating a Clock Driver (CKD) into a DDR5 DIMM provides numerous advantages, particularly in memory stability and performance, and enhances signal integrity and reliability at high speeds. By regenerating the clock signal locally on the DIMM, a CKD ensures stable operation even at elevated clock speeds. With a DDR5 CKD, DIMM data rates can be increased from 6400 Mbps to 7200 Mbps in the initial version of the standard, and targeting up to 9200 Mbps in future versions.
Integrating a Clock Driver (CKD) into a DDR5 DIMM provides numerous advantages, particularly in memory stability and performance, and enhances signal integrity and reliability at high speeds. By regenerating the clock signal locally on the DIMM, a CKD ensures stable operation even at elevated clock speeds. With a DDR5 CKD, DIMM data rates can be increased from 6400 Mbps to 7200 Mbps in the initial version of the standard, and targeting up to 9200 Mbps in future versions.
