
Arm Intros Cortex-A320 Armv9 CPU for IoT and Edge AI Applications
Arm's new Cortex-A320 represents its first ultra-efficient CPU using the advanced Armv9 architecture dedicated to the needs of IoT and AI applications. The processor achieves over 50% higher efficiency compared to the Cortex-A520 through several microarchitecture optimizations, together with a narrow fetch and decode data path, densely banked L1 caches, and a reduced-port integer register file. It also delivers 30% improved scalar performance compared with its predecessor, the Cortex-A35, via efficient branch predictors, pre-fetchers, and memory system improvements.
The Cortex-A320 is a single-issue, in-order CPU with a 32-bit instruction fetch and 8-stage pipeline. The processor offers scalability by supporting single-core to quad-core configurations. It features DSU-120T, a streamlined DynamIQ Shared Unit (DSU) which enables Cortex-A320-only clusters. Cortex-A320 supports up to 64 KB L1 caches and up to 512 KB L2, with a 256-bit AMBA5 AXI interface to external memory. The L2 cache and the L2 TLB can be shared between the Cortex-A320 CPUs. The vector processing unit, which implements the NEON and SVE2 SIMD (Single Instruction, Multiple Data) technologies, can be either private in a single core complex or shared between cores in dual-core or quad-core implementations.
The Cortex-A320 is a single-issue, in-order CPU with a 32-bit instruction fetch and 8-stage pipeline. The processor offers scalability by supporting single-core to quad-core configurations. It features DSU-120T, a streamlined DynamIQ Shared Unit (DSU) which enables Cortex-A320-only clusters. Cortex-A320 supports up to 64 KB L1 caches and up to 512 KB L2, with a 256-bit AMBA5 AXI interface to external memory. The L2 cache and the L2 TLB can be shared between the Cortex-A320 CPUs. The vector processing unit, which implements the NEON and SVE2 SIMD (Single Instruction, Multiple Data) technologies, can be either private in a single core complex or shared between cores in dual-core or quad-core implementations.