Another day, another Intel Tiger Lake and Xe graphics leak. This time, it comes courtesy of secret benchmark spotter extraordinaire TUM_APISAK, who spotted an Intel Tiger Lake CPU with integrated graphics on SiSoftware. Tiger Lake will ship with a graphics capability that reaches at least 96 Execution units (which boils down to the referred 768 Shading Units), which corresponds to the graphics prowess available on Intel's (currently discrete) DG1-SDV. The Iris Xe graphics on this benchmark are running at 1.3 GHz, with a 6.3 GB of memory on their elbow.

Intel's 10 nm Xe DG1 silicon made its first public appearance as the DG1-SDV (software development vehicle), a desktop PCIe graphics cards that Intel shipped out to its ISVs (independent software vendors), allowing them to begin preparing software for the Xe architecture. Argonne National Laboratory, the organization behind the Aurora Supercomputing Project that implements Xe HP "Ponte Vecchio" super-scalar compute processors, in its presentation, took a brief technical detour talking a bit about the DG1-SDV.

In the presentation, it is revealed that Intel will indeed monetize (or "productize") the silicon at the heart of the DG1-SDV, only not as a desktop graphics card. The chip will be sold as a mobile GPU, not even as an MXM, but as a GPU meant to be hardwired along with its dedicated memory onto notebooks' mainboards. We predict Intel is attempting to tap into the market segment where NVIDIA sells its GeForce MX300 line of entry-level discrete GPUs. Earlier this week, we spotted a discrete GPU with the specs of the DG1 having significantly increased 1.50 GHz GPU clocks, resulting in a FP32 throughput rivaling the AMD Radeon RX 560 or the "Vega" based iGPU of "Renoir." The Xe architecture will also be released as an iGPU solution, powering Intel's "Tiger Lake" Core mobile processor. Find the Aurora presentation here (PDF).

An Intel Gen12 Xe GPU, possibly a discrete- DG1 prototype, showed up on the SiSoft SANDRA online database. The GPU is detailed by SANDRA as having 768 unified shaders across 96 execution units (EUs), a 1.50 GHz GPU clock speed, 1 MB of on-die L2 cache, and 3 GB of dedicated video memory of an unknown type (likely GDDR6). This is probably a different chip from the DG1-SDV, which caps out at 900 MHz GPU clock, although its SIMD muscle is identical.

At a clock-speed of 1.50 GHz, the chip would feature an FP32 throughput of 2,303 GFLOPs (we know this from the DG1-SDV offering 1382 GFLOPs at 900 MHz). If the software-side optimization backs this hardware, the resulting product could end up with performance in the league of the 8 CU Radeon "Vega" solution found in the AMD "Renoir" APU, or the Radeon RX 560 discrete GPU, which are just about enough for PUBG at 1080p with medium settings.

A reportedly leaked Intel slide via DigitalTrends has given us a load of information on Intel's upcoming take on the high performance graphics accelerators market - whether in its server or consumer iterations. Intel's Xe has already been cause for much discussion in a market that has only really seen two real competitors for ages now - the coming of a third player with muscles and brawl such as Intel against the already-established players NVIDIA and AMD would surely spark competition in the segment - and competition is the lifeblood of advancement, as we've recently seen with AMD's Ryzen CPU line.

The leaked slide reveals that Intel will be looking to employ a Multi-Chip-Module (MCM) approach to its high performance "Arctic Sound" graphics architecture. The GPUs will be available in up to 4-tile configuration (the name Intel is giving each module), which will then be joined via Foveros 3D stacking (first employed in Intel Lakefield. This leaked slide shows Intel's approach starting with a 1-tile GPU (with only 96 of its 128 total EUs active) for the entry level market (at 75 W TDP) a-la DG1 SDV (Software Development Vehicle).