Details of what is claimed to be Google's upcoming Tensor G5 and G6 SoCs have popped up over on Notebookcheck.net and the site claims to have found the specs on a public platform, without going into any further details. Those that were betting on the Tensor G5—codenamed Laguna—delivering vastly improved performance over the Tensor G4, are likely to be disappointed, at least on the CPU side of things. As previous rumours have suggested, the chip is expected to be manufactured by TSMC, using its N3E process node, but the Tensor G5 will retain the single Arm Cortex-X4 core, although it will see a slight upgrade to five Cortex-A725 cores vs. the three Cortex-A720 cores of the Tensor G4. The G5 loses two Cortex-A520 cores in favour of the extra Cortex-A725 cores. The Cortex-X4 will also remain clocked at the same peak 3.1 GHz as that of the Tensor G4.

Interestingly it looks like Google will drop the Arm Mali GPU in favour of an Imagination Technologies DXT GPU, although the specs listed by Notebookcheck doesn't add up with any of the specs listed by Imagination Technologies. The G5 will continue to support 4x 16-bit LPDDR5 or LPDDR5X memory chips, but Google has added support for UFS 4.0 memory, something that's been a point of complaint for the Tensor G4. Other new additions is support for 10 Gbps USB 3.2 Gen 2 and PCI Express 4.0. Some improvements to the camera logic has also been made, with support for up to 200 Megapixel sensors or 108 Megapixels with zero shutter lag, but if Google will use such a camera or not is anyone's guess at this point in time.

A CPU-Z screenshot of an alleged Intel Core Ultra 9 285K "Arrow Lake-S" desktop processor engineering sample is doing rounds on social media, thanks to wxnod. CPU-Z identifies the chip with an Intel Core Ultra case badge with the deep shade of blue associated with the Core Ultra 9 brand extension, which hints at this being the top Core Ultra 9 285K processor model, we know it's the "K" or "KF" SKU looking at its processor base power reading of 125 W. The chip is built in the upcoming Intel Socket LGA1851. CPU-Z displays the process node as 7 nm, which corresponds with the Intel 4 foundry node.

Intel is using the same Intel 4 foundry node for "Arrow Lake-S" as the compute tile of its "Meteor Lake" processor. Intel 4 offers power efficiency and performance comparable to 4 nm nodes from TSMC, although it is physically a 7 nm node. Likewise, the Intel 3 node is physically 5 nm. If you recall, the main logic tile of "Lunar Lake" is being built on the TSMC N3P (3 nm) node. This means that Intel is really gunning for performance/Watt with "Lunar Lake," to get as close to the Apple M3 Pro as possible.

Last week, we got confirmation from the highest levels of Dell and NVIDIA that the latter is making a client PC processor for the Windows on Arm (WoA) AI PC ecosystem that only has one player in it currently, Qualcomm. Michael Dell hinted that this NVIDIA AI PC processor would be ready in 2025. Since then, speculation has been rife about the various IP blocks NVIDIA could use in the development of this chip, the two key areas of debate have been the CPU cores and the process node.

Given that NVIDIA is gunning toward a 2025 launch of its AI PC processor, the company could implement reference Arm IP CPU cores, such as the Arm Cortex X5 "Blackhawk," and not venture out toward developing its own CPU cores on the Arm machine architecture, unlike Apple. Depending on how the market recieves its chips, NVIDIA could eventually develop its own cores. Next up, the company could use the most advanced 3 nm-class foundry node available in 2025 for its chip, such as the TSMC N3P. Given that even Apple and Qualcomm will build their contemporary notebook chips on this node, it would be a logical choice of node for NVIDIA. Then there's graphics and AI acceleration hardware.

Some of the earliest signs are emerging that AMD's mobile processor or desktop APU silicon that succeeds "Strix Point" being codenamed "Sound Wave." AMD tends to come up with quirky internal codenames for upcoming projects, mostly to zero in on the source of leaks, so "Sound Wave" as a codename is subject to change with time. While the upcoming 4 nm "Strix Point" and "Strix Halo" chips implement the "Zen 5" CPU microarchitecture and RDNA 3+ graphics architecture, besides XDNA 2 based NPU with a generational tripling in AI TOPS; Wccftech believes that "Sound Wave" could be an AMD processor of comparable class to "Strix Point," which implements the "Zen 6" CPU microarchitecture, which AMD has planned for a 2025-26 timeframe.

Perhaps the most interesting aspect of this leak is the foundry node, with the original source over at Korean tech blog Gamma0burst referencing 3 nm. This is the final node family from TSMC to implement FinFET transistors before the foundry transitions to nanosheets with N2. It's likely that AMD chooses one of the more advanced variants of TSMC's 3 nm nodes, such as the N3P or N3X, because 2025-26 will see rival Intel get close to introducing the Intel 20A foundry node for mass-production. Not much else is known about "Sound Wave" besides the "Zen 6" CPU cores at this point.

TSMC's 2 nm-class foundry node, dubbed N2, will enter mass production only in 2025, a report by the Financial Times says. The premier Taiwan-based foundry has been reportedly showcasing TSMC N2 to its biggest customer for advanced nodes, Apple. The node will likely power Apple's in-house silicon that drives the iPhone 17 Pro and Pro Max devices that are slated for 2025. This implies that the current 3 nm class nodes from TSMC will continue to power Apple silicon into 2024 and its iPhone 16 Pro/Pro Max.

The current Apple A17 Pro and M3 chips powering the iPhone 15 Pro/Max and the H2-2023 Macs are based on TSMC's N3 node, with a 183 MTr/mm² transistor density. TSMC has four other 3 nm-class nodes, with the N3E node that just entered mass production to offer a jump to 215.6 MTr/mm², and its 2024 successor, the N3P, pushing transistor densities further up to 224 MTr/mm². TSMC's first 2 nm-class node, the N2, offers a jump to around 259 MTr/mm², which makes the N3P a nice halfway point for Apple between the N3 and N2, for its 2024 silicon.

TSMC today showcased its latest technology developments at its 2023 North America Technology Symposium, including progress in 2 nm technology and new members of its industry-leading 3 nm technology family, offering a range of processes tuned to meet diverse customer demands. These include N3P, an enhanced 3 nm process for better power, performance and density, N3X, a process tailored for high performance computing (HPC) applications, and N3AE, enabling early start of automotive applications on the most advanced silicon technology.

With more than 1,600 customers and partners registered to attend, the North America Technology Symposium in Santa Clara, California is the first of the TSMC's Technology Symposiums around the world in the coming months. The North America symposium also features an Innovation Zone spotlighting the exciting technologies of 18 emerging start-up customers.

TSMC today held a 3 nanometer (3 nm) Volume Production and Capacity Expansion Ceremony at its Fab 18 new construction site in the Southern Taiwan Science Park (STSP), bringing together suppliers, construction partners, central and local government, the Taiwan Semiconductor Industry Association, and members of academia to witness an important milestone in the Company's advanced manufacturing.

TSMC has laid a strong foundation for 3 nm technology and capacity expansion, with Fab 18 located in the STSP serving as the Company's GIGAFAB facility producing 5 nm and 3 nm process technology. Today, TSMC announced that 3 nm technology has successfully entered volume production with good yields, and held a topping ceremony for its Fab 18 Phase 8 facility. TSMC estimates that 3 nm technology will create end products with a market value of US$1.5 trillion within five years of volume production.

According to news out of Taiwan, TSMC will hold a ceremony to mark the official mass production start of its 3 nm node on the 29th of December. This is said to help "shatter doubts about de-Taiwanization" or in simpler terms, that Taiwan will lose its golden goose as TSMC invests abroad. The 3 nm fab—known as fab 18—is based in southern Taiwan's Tainan and the ceremony also marks the start of an expansion of TSMC's most advanced fab. TSMC is said to be kicking off its N3E node production sometime in the second half of 2023, followed by its N3P node in 2024, all of which should take place at fab 18, which also produces 5 nm wafers.

In related news, according to Reuters, a Japanese lawmaker from the ruling party has said that TSMC is considering a second plant in Japan, in addition to its current joint venture that is already under construction. TSMC's response to Reuters was that the company isn't ruling out Japan for future fabs, but that the company doesn't have any current plans. At the same time, TSMC is said to be sending executives to Dresden, Germany in early 2023, for a second round of talks about building a fab to help support the European auto industry, although this would be a 28/22 nm fab, which is far from cutting edge these days, although a lot more advanced than most fabs making chips for the auto industry.