Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, demonstrates its industry-leading 3 nm PCIe Gen 7 connectivity at the OCP Global Summit, October 15-17, at the San Jose Convention Center. PCIe Gen 7 doubles data transfer speeds, enabling continued scaling of compute fabrics inside accelerated server platforms, general-purpose servers, CXL systems and disaggregated infrastructure. Building on its widely deployed PAM4 technology and utilizing its industry-leading accelerated infrastructure silicon platform, Marvell has developed the industry's most comprehensive interconnect portfolio addressing all high-bandwidth optical and copper connections in AI data centers. This innovative portfolio empowers cloud data center operators to optimize their infrastructure for their specific architectures and workloads to meet the exponential demands of AI.

Marvell pioneered PAM4 technology over a decade ago and leads the industry in PAM4 interconnect shipments. Today, most of the optical interconnects used in data center backend and frontend networks are based on PAM4 technology. As compared to PCIe Gen 5, which was based on NRZ modulation, PCIe Gen 6 and 7 require the use of PAM4 modulation. With its recent PCIe Gen 6 retimer announcement and this PCIe Gen 7 demonstration, Marvell extends its industry-leading PAM4-based optical and copper interconnect portfolio beyond Ethernet and InfiniBand into copper and optical PCIe, CXL and proprietary compute fabric links.

Marvell Technology, Inc. (NASDAQ: MRVL), a leader in data infrastructure semiconductor solutions, today announced the development of FBNIC, a custom 5 nm network interface controller (NIC) ASIC in collaboration with Meta to meet the company's infrastructure and use case requirements. The FBNIC board design will also be contributed by Marvell to the Open Compute Project (OCP) community. FBNIC combines a customized network controller designed by Marvell and Meta, a co-designed board, and Meta's ASIC, firmware and software. This custom design delivers innovative capabilities, optimizes performance, increases efficiencies, and reduces the average time needed to resolve potential network and server issues.

"The future of large-scale, data center computing will increasingly revolve around optimizing semiconductors and other components for specific applications and cloud infrastructure architectures," said Raghib Hussain, President of Products and Technologies at Marvell. "It's been exciting to partner with Meta on developing their custom FBNIC on our industry-leading 5 nm accelerated infrastructure silicon platform. We look forward to the OCP community leveraging the board design for future innovations."

Credo Technology Group Holding Ltd (Credo), an innovator in providing secure, high-speed connectivity solutions that deliver improved energy efficiency as data rates and corresponding bandwidth requirements increase throughout the data infrastructure market, is excited to announce the company's first Toucan PCI Express (PCIe) 6, Compute Express Link (CXL) 3.x and Magpie PCIe 7, CXL 4.x retimers and OSFP-XD 16x 64GT/s (1 Tb) PCIe 6/CXL HiWire AECs. Credo will demonstrate the Toucan PCIe 6 retimers and HiWire AECs at the upcoming Open Compute Project (OCP) Summit October 15-17 in Booth 31 and the OCP Innovation Center.

Building on Credo's renowned Serializer/Deserializer (SerDes) technology, the new PCIe 6 and PCIe 7 retimers deliver industry-leading performance and power efficiency while being built on lower cost, more mature process nodes than competing devices. Credo will also include enhanced diagnostic tools, including an embedded logic analyzer and advanced SerDes tools driven by a new GUI designed to enable rapid bring up and debug of customer systems.

Marvell Technology, a leader in data infrastructure semiconductor solutions, today expanded its connectivity portfolio with the launch of the new Alaska P PCIe retimer product line built to scale data center compute fabrics inside accelerated servers, general-purpose servers, CXL systems and disaggregated infrastructure. The first two products, 8- and 16-lane PCIe Gen 6 retimers, connect AI accelerators, GPUs, CPUs and other components inside server systems.

Artificial intelligence (AI) and machine learning (ML) applications are driving data flows and connections inside server systems at significantly higher bandwidth, necessitating PCIe retimers to meet the required connection distances at faster speeds. PCIe is the industry standard for inside-server-system connections between AI accelerators, GPUs, CPUs and other server components. AI models are doubling their computation requirements every six months1 and are now the primary driver of the PCIe roadmap, with PCIe Gen 6 becoming a requirement.

Introspect Technology, a JEDEC member and a leading manufacturer of test and measurement instruments, announced today that it has shipped the M5512 GDDR7 Memory Test System, the world's first commercial solution for testing JEDEC's newly minted JESD239 Graphics Double Data Rate (GDDR7) SGRAM specification. This category-creating solution enables graphics memory engineers, GPU design engineers, product engineers in both memory and GPU spaces, and system integrators to rapidly bring up new GDDR7 memory devices, debug protocol errors, characterize signal integrity, and perform detailed memory read/write functional stress testing without requiring any other tool.

The GDDR7 specification is the latest industry standard that is aimed at the creation of high-bandwidth and high-capacity memory implementations for graphics processing, artificial intelligence (AI), and AI-intensive networking. Featuring pulse-amplitude modulation (PAM) and an improved signal to noise ratio compared to other PAM4 standards used in networking, the GDDR7 PAM3 modulation technology achieves greater power-efficiency while significantly increasing data transmission bandwidth over constrained electrical channels.

Artificial intelligence has been a hot topic this year, and everything is now an AI processor, from CPUs to GPUs, NPUs, and many others. However, it was only a matter of time before we saw an integration of AI processing elements into the networking chips. Today, Broadcom announced its new Ethernet switching silicon called Trident 5-X12. The Trident 5-X12 delivers 16 Tb/s of bandwidth, double that of the previous Trident generation while adding support for fast 800G ports for connection to Tomahawk 5 spine switch chips. The 5-X12 is software-upgradable and optimized for dense 1RU top-of-rack designs, enabling configurations with up to 48x200G downstream server ports and 8x800G upstream fabric ports. The 800G support is added using 100G-PAM4 SerDes, which enables up to 4 m DAC and linear optics.

However, this is not only a switch chip on its own. Broadcom has added AI processing elements in an inference engine called NetGNT (Networking General-purpose Neural-network Traffic-analyzer). It can detect common traffic patterns and optimize data movement across the chip. Specifically, the company has listed an example of the system doing AI/ML workloads. In that case, NetGNT performs intelligent traffic analysis to avoid network congestion in these workloads. For example, it can detect the so-called "incast" patterns in real-time, where many flows converge simultaneously on the same port. By recognizing the start of incast early, NetGNT can invoke hardware-based congestion control techniques to prevent performance degradation without added latency.

PCI-SIG is pleased to share the PCI Express (PCIe) 7.0 specification, version 0.3 is now available to members. Version 0.3 of the specification indicates that the first review draft of the specification is complete and has received work group approval. This is an important milestone for PCI-SIG, demonstrating we are on plan for a full specification release in 2025.

The PCIe 7.0 specification is targeted to support emerging applications such as 800 G Ethernet, AI/ML, Cloud and Quantum Computing; and data-intensive markets like Hyperscale Data Centers, High-Performance Computing (HPC), Edge and Military/Aerospace.

Molex, a company known for making various electronics and connectors, has today announced that the company has developed a first-of-its-kind chip-to-chip connector. Designed mainly for the data center, the Molex 224G product portfolio includes next-generation cables, backplanes, board-to-board connectors, and near-ASIC connector-to-cable solutions. Running at 224 Gbps speeds, these products use PAM4 signaling and boast with " highest levels of electrical, mechanical, physical and signal integrity." As the company states, future high-performance computing (HPC) data centers require a lot of board-to-board, chip-to-chip, and other types of communication to improve overall efficiency and remove bottlenecks in data transfer. To tackle this problem, Molex has a range of products, including Mirror Mezz Enhanced, Inception, and CX2 Dual Speed products.

Future generative AI, 1.6T (1.6 Tb/s) Ethernet, and other data center challenges need a dedicated communication standard, which Molex is aiming to provide. Working with various data center and enterprise customers, the company claims to have set the pace for products based on this 224G PAM4 chip-to-chip technology. We suspect that Open Compute Project (OCP) will be first in the line of adoption, ad Molex has historically worked with them as they adopted Mirror Mezz and Mirror Mezz Pro board-to-board connectors. The new products can be seen below, and we expect to hear more announcements from Molex's partners. Solutions like OSFP 1600, QSFP 800, and QSFP-DD 1600 already use 224G products.