AMD's openSIL project, aimed towards open CPU silicon initialization code, continues progressing despite a slight delay in its development timeline. The initiative, which will eventually replace the current AGESA system across AMD's client and server processors, received a new update. The company initially targeted the end of 2024 to release proof-of-concept code for Phoenix client SoCs and Turin server hardware. However, as we move through the first quarter of 2025, AMD has acknowledged a slight deviation from this schedule. In a recent statement, AMD representatives assured the developer community that work continues steadily on both Phoenix and Turin proof-of-concept releases.

"We are hard at work preparing the Phoenix and Turin POC's for public release," stated an AMD representative, emphasizing that these releases will serve as sample code previewing future production-worthy implementations. The company clarified that these initial releases are not intended for production environments. The delay has minimal impact on AMD's plan, as the primary goal remains focused on achieving full production readiness with the upcoming Zen 6 architecture. The openSIL project promises to enhance Coreboot support and provide developers with full access to low-level system components. Though limited to select reference motherboards, the proof-of-concept releases will serve as the first milestones in AMD's journey toward more open hardware solutions.

OpenSIL is an open-source CPU initialization framework project that seeks to replace on-chip initialization microcode, such as AGESA, across both client- and server processors. AMD looks to implement OpenSIL as it makes its AMD EPYC processors more friendly to large customers that want to take control of this aspect of the processor. Since its open-sourcing in June 2023, AMD has come up with reference motherboards implementing OpenSIL, as well as modifying a Supermicro server motherboard to the architecture, to demo at conferences. AMD firmware engineer Paul Grimes presented the company's progress with implementing OpenSIL, at the OSFC conference, in Germany. It's been known that AMD is targeting a 2025-26 timeline for OpenSIL to hit product, but AMD put out specifics, such as its next-generation "Venice" server processor supporting OpenSIL.

"Venice" is codename for an AMD EPYC server processor generation succeeding "Turin." It is built on the future "Zen 6" microarchitecture, and AMD could at least unveil the processor some time in 2025, if not mass-produce it. late-2024 thru 2025 could see the company ramp up "Turin" and other server processors implementing "Zen 5." That's not all, AMD plans to being OpenSIL even to client processors, with the generation of Ryzen processors based on "Zen 6." This will see the AGESA microcode replaced by a first-party firmware from AMD based on OpenSIL, which PC OEMs will be able to customize. The biggest impact of this change will be felt in the commercial notebook and commercial desktop segments, where large organizations can take greater control over the chip initialization firmware.

During the OCP Regional Summit, AMD has shared plans to replace AGESA with openSIL. The change will not come soon, and according to details, it will be a slow process starting in 2026. AGESA firmware updates are quite important but also vulnerable to cyber-attacks, which is one of the key points for the new OpenSIL, which is proposed as an open-source solution.

As detailed by Phoronix, AMD mentioned the Open-Source Silicon Initialization Library (openSIL) back in mid-April, when it launched initial support for 4th Gen EPYC processors and its reference platform. Although initially aimed at server processors, AMD has made clear during the OCP presentation that the OpenSIL is meant to be a replacement to AMD Generic Encapsulated Software Architecture (AGESA), covering the entire product stack. As said, AMD plans for openSIL to be simple, easily scalable, lightweight, and open-source, thus increasing the overall security.