The "Zen" Architecture

The oldest reports about AMD working on the "Zen" architecture date back to 2012, when AMD re-hired CPU core designer Jim Keller, credited with the original winning K8 and K9 architecture designs, to work on a new core architecture to succeed "Bulldozer." AMD continued to invest in the "Bulldozer" IP in the form of incremental core updates, hoping that trends in the software industry towards parallelization would improve, giving it a big break in price/performance. Those trends, in the form of DirectX 12 and Vulkan 3D APIs being multi-core friendly, came in a tad late (towards late 2016). Four years of work by a team dedicated to its development, led by Jim Keller, resulted in the "Zen" core.


At the heart of the "Zen" core are two very important innovations - a very "intelligent" branch-prediction system that uses neural nets (yes, of the same kind that power deep-learning machinery) to predict branches in code and load the most appropriate instructions and allocation of core resources; and there's a 1.5X increase in issue width and execution resources, besides a 1.75X increase in the instruction scheduler window. Intel had been beating AMD in core performance and efficiency in exactly these two areas, and AMD finally addressed it instead of throwing in many more hardware resources without addressing the branch-prediction issues. "Zen" also features an up-to-date ISA instruction set including AVX2, FMA3, and SHA.


All Ryzen processors are based on the 14 nm "Summit Ridge" silicon built at GlobalFoundries' swanky new facility in Upstate New York. One look at the die shot will show you that the CPU cores are clumped into two groups each. One such group is called a quad-core complex (CCX). There is no specific reason as to why AMD chose groups of four cores, other than four being a manageable number of cores for AMD's product managers. Each individual core in a CCX can be disabled and doesn't share anything with its neighboring core except for an 8 MB block of L3 cache. Each core has its own dedicated 512 KB L2 cache. The two CCX units talk to each other over AMD Infinity Fabric, a new high-bandwidth interconnect that succeeds HyperTransport. For the Ryzen 3 1200, AMD disabled two cores per CCX and reduced the L3 cache amount to 4 MB per CCX.

The AM4 Platform

What sets "Summit Ridge" apart from Intel dies, such as "Kaby Lake," is that it is a full-fledged SoC (system-on-chip). It integrates both the northbridge and southbridge. In addition to memory and PCIe, socket AM4 processors also put out USB 3.0 and two SATA 6 Gb/s ports. The platform still has something called a "chipset," but it only serves to increase connectivity options, such as adding more SATA ports, USB 3.1 ports, and a few more general-purpose PCIe lanes. On Intel's platforms, the PCH (platform controller hub) serves the functions of the southbridge, while the northbridge is fully integrated with the processor.



AMD has five chipsets for Ryzen - the X370 for high-end desktops, which supports proprietary multi-GPU technologies such as NVIDIA SLI, the mid-tier B350 chipset with a slimmer connectivity feature set, and the entry-level A320 chipset for low-cost desktops. There's also the X300 and A300. We doubt you can even call these a chipset because they don't even have an A-link chipset bus to the SoC and only talk over legacy SPI pins, and they have simple components to keep the platform ticking. What sets the two apart is the lack of CPU overclocking support on the A300. On machines with the X300 and A300 (such as SFF desktops), all the connectivity is handled by the SoC.