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Spoiler: Intel Socket 1851 DDR5 Tweaking
Intel's new generation has launched, bringing significant changes to DDR5 memory. A notable addition is CUDIMMs, which make previously unimaginable frequencies a reality. Memory speeds beyond 8000 MT/s are now achievable, though utilizing these higher frequencies will likely require CUDIMMs. For the highest DDR5 speeds 9000 MT/s and beyond, 2-slot motherboards will once again become a crucial component.
Since the Intel-supported Ultra 200 series CPUs are still new, the process of overclocking and finding workarounds for each platform's quirks is still evolving. As a result, this comparison focuses solely on the stock XMP profile versus a manually tweaked version of the same memory kit. First, we apply the base XMP profile, allowing the motherboard to set all sub-timings not included in the SPD data. Next, we manually lower the sub-timings while keeping the XMP primary timings and voltage unchanged. Finally, we increase the CPU Ring Cache and Die-to-Die (D2D) ratio to further reduce latency while maintaining the newly adjusted sub-timings.
Intel Results
Shooting completely in the dark for this overclock, there was no reference to what is "suppose" to work. Once again a tedious, methodical process of changing each value and validating if, in fact, it was stable for long periods of time was the only option. This does not guarantee 24/7 stability, but it is enough for a normal home computer use-case. These results below were validated to pass y-cruncher 2.5B and reach 6000% or higher in the memory stress testing software Karhu. Because of this longer stability test, temperatures can become a big factor and this required a fan placed on top of the memory to minimize issues. Lots of additional small adjustments could have been made to the secondary and tertiary timings, but would likely be harder to stabilize in the long run.
At this early stage, it's difficult to determine what's normal for CUDIMM, but in our testing, the Corsair Vengeance kit did not respond well to increased voltage. Any DRAM VDDQ setting above 1.45 V resulted in a boot failure, though DRAM VDD tolerated higher voltages without issue. Additionally, we found tFAW and tWRWR_sg to be particularly sensitive to change, leading to slightly higher sub-timings than initially expected.
The biggest performance gains came from increasing the Ring Cache and Die-to-Die (D2D) ratio, along with optimizing memory sub-timings, all without needing to adjust voltage. However, this process was slow, with many failed attempts stemming from trying to combine these adjustments into a single overclock. It's clear that the Intel Ultra 200 series has a memory latency issue, but with manual tuning, significant improvements can be achieved.
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