The Compute Tile

The Compute tile is where the all important CPU cores are located. This tile is built on the latest Intel 4 foundry node, and contains four distinct components. Among these are the Performance Cores or P-cores, the Efficiency Cores or E-cores, an L3 cache, and the ringbus interconnect for the compute tile.


With "Meteor Lake," Intel is introducing the new "Redwood Cove" performance core. The company is looking to offer a generational increase in IPC, clock speeds, and ISA capabilities compared to the current "Raptor Cove" P-cores. The largest Compute tile possible for "Meteor Lake," has no more than six P-cores.


Besides the six P-cores, the Compute tile contains two E-core clusters, each with four cores. Intel is introducing the new "Crestmont" E-core with "Meteor Lake," which the company claims will offer a performance/Watt increase, and an IPC increase, over the current "Gracemont" E-core. While the "Redwood Cove" P-core supports SMT (HyperThreading), the E-cores remain 1 logical processor per core.

The "Redwood Cove" P-cores each has a dedicated L2 cache, while each of the two "Crestmont" E-core clusters has an L2 cache that they share among their four cores. The E-core clusters and the P-cores share a unified L3 cache that's exclusive to the Compute tile.

The SoC Tile

The SoC Tile is a very versatile, centrally located tile that contains various components from what traditionally constituted the "uncore" or the part of the processor other than the cores. Among these are the all important memory controller, the NPU accelerating AI Boost, the media accelerator, the image processing engine, the display controller, and the I/O interface.


The tile has two distinct kinds of fabrics depending on the kind of device being interconnected. Intel developed network-on-chip (NOC), a low-latency coherent fabric connecting the various high-bandwidth devices on the SoC tile.


The I/O fabric interconnects various on-chip devices that would have traditionally ended up in the discrete PCH. These include network controllers, security silicon, management engine, USB controllers, SATA controllers, and audio controllers. The I/O fabric is essentially the PCI-Express root complex of the processor, with each of the I/O controllers being connected to it as they would on a PCH. An off-shoot of the I/O fabric leads to the I/O tile, which contains the processor's PCI-Express PHY, USB4 controller, and Thunderbolt interface.

Low Power Island E-cores?

With "Meteor Lake," Intel is introducing a three-tiered CPU core hierarchy. The Compute tile contains the P-cores and E-core clusters sharing an L3 cache, but there's an additional E-core cluster located on the SoC tile, called the Low Power Island E-cores. Based on the same "Crestmont" core architecture as the E-cores on the Compute tile although not being part of its ringbus or sharing its L3 cache; this E-core cluster has its own L2 cache shared among four cores.


The Low Power Island E-cores are very much part of the processor's core-count, are exposed as logical processors to the OS, and you can monitor them in your Windows Task Manager. They have the same ISA as the E-cores from the Compute tile.


There are two distinct needs to be fulfilled with having a small number of E-cores located on the SoC tile. First, it puts x86 cores in the vicinity of the other on-die controllers, especially the NPU, and second, it allows Intel to power down the Compute tile when not needed, letting the machine idle at a very low power state.

The I/O Tile

The I/O tile contains the physical layer interfaces of the processor's PCI-Express interface, as well as PCIe-derivative interfaces such as Thunderbolt and USB4. The I/O tile is essentially an extension of the SoC tile. Intel felt the need for a separate I/O tile because that would allow them to use I/O tiles of different sizes to cater to different processor models. The I/O tile in the presentation is of its top configuration, with the most PCIe lanes, USB4, and Thunderbolt interfaces Intel intends to offer with "Meteor Lake," although some of the lower-end SKUs could be configured with fewer PCIe lanes, and lacking Thunderbolt, using a physically smaller I/O tile. It's not just the I/O tile, there could be variants of the Compute tile with fewer numbers of P-cores, resulting in physically smaller tiles.

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