Samsung Electronics Co., Ltd., announced today that it has begun mass producing the industry's first 4-gigabyte (GB) DRAM package based on the second-generation High Bandwidth Memory (HBM2) interface, for use in high performance computing (HPC), advanced graphics and network systems, as well as enterprise servers. Samsung's new HBM solution will offer unprecedented DRAM performance - more than seven times faster than the current DRAM performance limit, allowing faster responsiveness for high-end computing tasks including parallel computing, graphics rendering and machine learning.

"By mass producing next-generation HBM2 DRAM, we can contribute much more to the rapid adoption of next-generation HPC systems by global IT companies," said Sewon Chun, senior vice president, Memory Marketing, Samsung Electronics. "Also, in using our 3D memory technology here, we can more proactively cope with the multifaceted needs of global IT, while at the same time strengthening the foundation for future growth of the DRAM market."

The newly introduced 4GB HBM2 DRAM, which uses Samsung's most efficient 20-nanometer process technology and advanced HBM chip design, satisfies the need for high performance, energy efficiency, reliability and small dimensions making it well suited for next-generation HPC systems and graphics cards.

The fourth generation of AMD Graphics CoreNext GPU architecture has been reportedly codenamed "Polaris" by the company. It makes its debut later this year in the company's "Arctic Islands" GPUs, built on Samsung's 14 nm FinFET node. According to the company, Polaris will provide a "historic leap in performance/Watt" for Radeon GPUs. Chips based on Polaris will feature improvements to not just the compute units, but will also come with generational improvements to pretty much every other component, including a new front-end, display controllers, and a new memory controller supporting HBM2.

AMD debuted its first generation GCN architecture with the Radeon HD 7000 series, notably the "Tahiti" silicon. Its second-generation, GCN 2.0, (reported in the press as GCN 1.1), debuted with the R9 290 series, notably the "Hawaii" silicon. The third-generation, GCN 3.0 (reported in the press as GCN 1.2), debuted with the R9 285, notably the "Tonga" silicon; making "Polaris" the fourth-generation. GCN 4.0 will form the core micro-architecture of the "Arctic Islands" family of GPUs, which make their debut in mid-2016.

NVIDIA revealed more details of its upcoming "Pascal" GPU architecture at the Japanese edition of the Graphics Technology Conference. The architecture will be designed to nearly double performance/Watt over the current "Maxwell" architecture, by implementing the latest tech. This begins with stacked HBM2 (high-bandwidth memory 2). The top "Pascal" based product will feature four 4-gigabyte HBM2 stacks, totaling 16 GB of memory. The combined memory bandwidth for the chip will be 1 TB/s. Internally, bandwidths can touch as high as 2 TB/s. The chip itself will support up to 32 GB of memory, and so enterprise variants (Quadro, Tesla), could max out the capacity. The consumer GeForce variant is expected to serve up 16 GB.

It's also becoming clear that NVIDIA will build its "Pascal" chips on the 16 nanometer FinFET process (AMD will build its next-gen chips on more advanced 14 nm process). NVIDIA is innovating a new interconnect called NVLink, which will change the way the company has been building dual-GPU graphics cards. Currently, dual-GPU cards are essentially two graphics cards on a common PCB, with PCIe bandwidth from the slot shared by a bridge-chip, and an internal SLI bridge connecting the two GPUs. With NVLink, the two GPUs will be interconnected with an 80 GB/s bi-directional data path, letting each GPU directly address memory controlled by the other. This should greatly improve memory management in games that take advantage of newer APIs such as DirectX 12 and Vulkan; and prime the graphics card for higher display resolutions. NVIDIA is expected to launch its first "Pascal" based products in the first half of 2016.

NVIDIA's next-generation flagship graphics processor, codenamed "GP100," has reportedly graduated to testing phase. That is when a limited batch of completed chips are sent from the foundry partner to NVIDIA for testing and evaluation. The chips tripped speed-traps on changeover airports, on their way to NVIDIA. 3DCenter.org predicts that the GP100, based on the company's "Pascal" GPU architecture, will feature no less than 17 billion transistors, and will be built on the 16 nm FinFET+ node at TSMC. The GP100 will feature an HBM2 memory interface. HBM2 allows you to cram up to 32 GB of memory. The flagship product based on GP100 could feature about 16 GB of memory. NVIDIA's design goal could be to squeeze out anywhere between 60-90% higher performance than the current-generation flagship GTX TITAN-X.

NVIDIA's next-generation GPUs, based on the company's "Pascal" architecture, will be reportedly built on the 16 nanometer FinFET node at TSMC, and not the previously reported 14 nm FinFET node at Samsung. Talks of foundry partnership between NVIDIA and Samsung didn't succeed, and the GPU maker decided to revert to TSMC. The "Pascal" family of GPUs will see NVIDIA adopt HBM2 (high-bandwidth memory 2), with stacked DRAM chips sitting alongside the GPU die, on a multi-chip module, similar to AMD's pioneering "Fiji" GPU. Rival AMD, on the other hand, could build its next-generation GCNxt GPUs on 14 nm FinFET process being refined by GlobalFoundries.

AMD published a paper with the IEEE for a new high-density computing device concept, which it calls the Exascale Heterogenous Processor or (EHP). It may be a similar acronym to APU (accelerated processing unit), but is both similar and different to it in many ways, which make it suitable for high-density supercomputing nodes. The EHP is a chip that has quite a bit in common with the recently launched "Fiji" GPU, that drives the company's flagship Radeon R9 Fury X graphics card.

The EHP is a combination of a main die, housing a large number of CPU cores, a large GPGPU unit, and an interposer, which connects the main die to 32 GB of HBM2 memory that's on-package, and is used as both main-memory and memory for the integrated GPGPU unit, without memory partitioning, using hUMA (heterogeneous unified memory access). The CPU component consists of 32 cores likely based on the "Zen" micro-architecture, using eight "Zen" quad-core subunits. There's no word on the CU (compute unit) count of the GPGPU core. The EHP in itself will be highly scalable. AMD hopes to get a working sample of this chip out by 2016-17.

Sources tell 3DCenter.org that NVIDIA has successfully taped out its next big silicon based on its upcoming "Pascal" GPU architecture, codenamed GP100. A successor to GM200, this chip will be the precursor to several others based on this architecture. A tape-out means that the company has successfully made a tiny quantity of working prototypes for internal testing and further development. It's usually seen as a major milestone in a product development cycle.

With "Pascal," NVIDIA will pole-vault HBM1, which is making its debut with AMD's "Fiji" silicon; and jump straight to HBM2, which will allow SKU designers to cram up to 32 GB of video memory. 3DCenter.org speculates that GP100 could feature anywhere between 4,500 to 6,000 CUDA cores. The chip will be built on TSMC's upcoming 16 nanometer silicon fab process, which will finally hit the road by 2016. The GP100, and its companion performance-segment silicon, the GP104 (successor to GM204), are expected to launch between Q2 and Q3, 2016.

AMD's next-generation GPU family, which it plans to launch some time in 2016, codenamed "Arctic Islands," will see the company skip the 20 nanometer silicon fab process from 28 nm, and jump straight to 14 nm FinFET. Whether the company will stick with TSMC, which is seeing crippling hurdles to implement its 20 nm node for GPU vendors; or hire a new fab, remains to be seen. Intel and Samsung are currently the only fabs with 14 nm nodes that have attained production capacity. Intel is manufacturing its Core "Broadwell" CPUs, while Samsung is manufacturing its Exynos 7 (refresh) SoCs. Intel's joint-venture with Micron Technology, IMFlash, is manufacturing NAND flash chips on 14 nm.

Named after islands in the Arctic circle, and a possible hint at the low TDP of the chips, benefiting from 14 nm, "Arctic Islands" will be led by "Greenland," a large GPU that will implement the company's most advanced stream processor design, and implement HBM2 memory, which offers 57% higher memory bandwidth at just 48% the power consumption of GDDR5. Korean memory manufacturer SK Hynix is ready with its HBM2 chip designs.