During the 69th annual IEEE International Electron Devices Meeting (IEDM), Intel demonstrated some of its latest transistor design and manufacturing advancements. The first one in line is the 3D integration of transistors. According to Intel, the company has successfully stacked complementary field effect transistors (CFET) at a scaled gate pitch down to 60 nm. With CFETs promising thinner gate channels, the 3D stacked CFET would allow for higher density by going vertically and horizontally. Intel's 7 node has a 54 nm gate pitch, meaning CFETs are already close to matching production-ready nodes. With more time and development, we expect to see 3D stacked CFETs in the production runs in the coming years.

Next, Intel has demonstrated RibbonFET technology, a novel approach that is the first new transistor architecture since the introduction of FinFET in 2012. Using ribbon-shaped channels surrounded by the gate, these transistors allow for better control and higher drive current at all voltage levels. This allows faster transistor switching speeds, which later lead to higher frequency and performance. The width of these nanoribbon channels can be modulated depending on the application, where low-power mobile applications use less current, making the channels thinner, and high-performance applications require more current, making the channels wider. One stack of nanoribbons can achieve the same drive current as multiple fins found in FinFET but at a smaller footprint.

Marking a milestone in Intel's ongoing manufacturing expansion in Arizona, the company today announced that the initial portion of the cleanroom is "weather tight" and the "blow down" phase has begun at the company's two new leading-edge chip factories on its Ocotillo campus in Chandler, Arizona. This milestone underscores Intel's dedication to advancing its presence in the state and fostering technological innovation.

"Our commitment to Arizona runs deep, and as we expand our operations, we remain dedicated to addressing the growing demand for semiconductors and helping the United States regain its leadership position in this vital industry. This milestone represents the result of great teamwork, proficient teams and exceptional craftsmanship of the tradespeople, and it's thanks to their hard work that we've made such significant progress on our site while keeping our culture of caring and the safety of all as our top priority." -Dan Doron, Intel vice president and general manager of Fab Construction Enterprise

What's New: Intel today announced one of the industry's first glass substrates for next-generation advanced packaging, planned for the latter part of this decade. This breakthrough achievement will enable the continued scaling of transistors in a package and advance Moore's Law to deliver data-centric applications.

"After a decade of research, Intel has achieved industry-leading glass substrates for advanced packaging. We look forward to delivering these cutting-edge technologies that will benefit our key players and foundry customers for decades to come."
-Babak Sabi, Intel senior vice president and general manager of Assembly and Test Development

Intel Corporation today reported second-quarter 2023 financial results. "Our Q2 results exceeded the high end of our guidance as we continue to execute on our strategic priorities, including building momentum with our foundry business and delivering on our product and process roadmaps," said Pat Gelsinger, Intel CEO. "We are also well-positioned to capitalize on the significant growth across the AI continuum by championing an open ecosystem and silicon solutions that optimize performance, cost and security to democratize AI from cloud to enterprise, edge and client."

David Zinsner, Intel CFO, said, "Strong execution, including progress towards our $3 billion in cost savings in 2023, contributed to the upside in the quarter. We remain focused on operational efficiencies and our Smart Capital strategy to support sustainable growth and financial discipline as we improve our margins and cash generation and drive shareholder value." In the second quarter, the company generated $2.8 billion in cash from operations and paid dividends of $0.5 billion.

Today, Intel announced a strategic collaboration agreement with Ericsson to utilize Intel's 18A process and manufacturing technology for Ericsson's future next-generation optimized 5G infrastructure. As part of the agreement, Intel will manufacture custom 5G SoCs (system-on-chip) for Ericsson to create highly differentiated leadership products for future 5G infrastructure. Additionally, the companies will expand their collaboration to optimize 4th Gen Intel Xeon Scalable processors with Intel vRAN Boost for Ericsson's Cloud RAN (radio access network) solutions to help communications service providers increase network capacity and energy efficiency while gaining greater flexibility and scalability.

"As our work together evolves, this is a significant milestone with Ericsson to partner broadly on their next-generation optimized 5G infrastructure. This agreement exemplifies our shared vision to innovate and transform network connectivity, and it reinforces the growing customer confidence in our process and manufacturing technology," said Sachin Katti, senior vice president and general manager of the Network and Edge group at Intel. "We look forward to working together with Ericsson, an industry leader, to build networks that are open, reliable and ready for the future."

Intel is about to turn chipmaking upside down with PowerVia, a new approach to delivering power that required a radical rethink to both how chips are made and how they are tested. For all the modern history of computer chips, they've been built like pizzas—from the bottom up, in layers. In the case of chips, you start with the tiniest features, the transistors, and then you build up increasingly less-tiny layers of wires that connect the transistors and different parts of the chip (these are called interconnects). Included among those top layers are the wires that bring in the power that makes the chip go.

When the chip is done, you flip it over, enclose it in packaging that provides connections to the outer world, and you're ready to put it in a computer. Unfortunately, this approach is running into problems. As they get smaller and denser, the layers that share interconnects and power connections have become an increasingly chaotic web that hinders the overall performance of each chip. Once an afterthought, "now they have a huge impact," says Ben Sell, vice president of Technology Development at Intel and part of the team that brought PowerVia to fruition. In short, power and signals fade, requiring workarounds or simply dumping more power in.