Over the weekend, there have been a series of leaks from sources such as Golden Pig Upgrade, and High Yield YT, surrounding Intel's next-generation desktop processor, the Core Ultra 2-series "Arrow Lake-S." The lineup is likely to continue the new client processor naming scheme Intel introduced with the Core Ultra 1-series "Meteor Lake" on the mobile platform. "Arrow Lake-S" is rumored to debut the new Socket LGA1851, which retains cooler-compatibility with LGA1700. Although Intel has nucleated all I/O functions of the traditional PCH to "Meteor Lake," making it a single-chip solution on the mobile platform; and although the mobile "Arrow Lake" will continue to be single-chip; the desktop "Arrow Lake-S" will be a 2-chip solution. This is mainly because the desktop platform demands a lot more PCIe lanes, for a larger number of NVMe storage devices, or high bandwidth devices such as Thunderbolt and USB4 hubs, etc.

Another key finding in this latest series of leaks, is that unlike "Meteor Lake," the desktop "Arrow Lake-S" will do away with low-power island E-cores located in the SoC tile of the processor. All CPU cores are located in the Compute tile, which is expected to be built in the Intel 20A foundry node—the company's first node to implement GAAFETs (nanosheets), with backside power delivery; as well as an advanced 2nd generation EUV lithography. Intel's 1st Gen EUV is used on the current FinFET-based Intel 4 and Intel 3 foundry nodes.

Feast your eyes on the first pictures of an Intel "Granite Rapids" Xeon processor wafer, courtesy of Andreas Schilling with HardwareLuxx.de. This is Intel's first commercial silicon built on the new Intel 3 foundry node, which is expected to be the company's final silicon fabrication node to implement FinFET technology; before the company switches to Nanosheets with the next-generation Intel 20A. Intel 3 offers transistor densities and performance competitive to TSMC N3 series, and Samsung 3GA series nodes.

The wafer contains square 30-core tiles, two of which make up a "Granite Rapids-XCC" processor, with CPU core counts going up to 56-core/112-threads (two cores left unused per tile for harvesting). Each of the 30 cores on the tile is a "Redwood Cove" P-core. In comparison, the current "Emerald Rapids" Xeon processor uses "Raptor Cove" cores, and is built on the Intel 7 foundry node. Intel is planning to overcome the CPU core-count deficit to AMD EPYC, including the upcoming EPYC "Turin" Zen 5 processors with their rumored 128-core/256-thread counts, by implementing several on-silicon fixed-function accelerators that speed up popular kinds of server workloads. The "Redwood Cove" core is expected to be Intel's first IA core to implement AVX10 and APX.

On December 14 Intel launched its first generation Core Ultra "Meteor Lake" line of mobile processors, and here is a a brief overview of the various processor models on offer at launch, thanks to a compilation by ComputerBase.de. "Meteor Lake" is Intel's first completely disaggregated processor, in which its numerous components are broken up into chiplets fabricated on different foundry nodes that strike the right performance/Watt suitable to the component, all held together by Intel's Foveros packaging technology (an evolution in multi-chip modules with a design focus on reducing inter-chiplet latencies to levels comparable to components on a monolithic chip). "Meteor Lake" also introduces a 3-tiered heterogeneous CPU architecture, with the introduction of the low-power island CPU cores.

Intel's mobile processor lineup is broadly categorized into the U-segment, targeting thin-and-light and ultraportable devices; and the H-segment, targeting notebooks of conventional thickness. At launch, the Core Ultra H-segment, and U-segment processors will coexist with P-segment processor models from the 13th Gen Core "Raptor Lake" series; as well as the upcoming 14th Gen Core "Raptor Lake Refresh" HX-segment. The P-segment is positioned between the U- and H-segments, targeting a class of devices that either what to be thin-and-light mainstream notebooks, or higher performance ultraportables. The HX-segment caters to high performance gaming notebooks and mobile workstations.

Late last year, it was reported that Intel is skipping its upcoming "Meteor Lake" microarchitecture for the desktop platform, giving it a mobile-platform debut in late-2023, with "Arrow Lake" following on in 2024, which would address both platforms. In the interim, Intel was expected to release a "Raptor Lake Refresh" architecture for desktop in 2023. It turns out now, that both the "Raptor Lake Refresh" and "Meteor Lake" architectures are coming to desktop—we just don't know when.

Apparently, Intel will brazen it out against AMD with a maximum CPU core-count of just 6 performance cores and 16 efficiency cores possible for "Meteor Lake." It's just that both the P-cores and a E-cores get an IPC uplift with "Meteor Lake." The processor features up to six "Redwood Cove" P-cores with an IPC uplift over the current "Raptor Cove" cores; and introduce the new "Crestmont" E-cores. A lot will depend on the IPC uplift of the latter. Leaf_hobby, a reliable source with Intel leaks on social media, has some interesting details on the I/O capabilities of "Meteor Lake" on the desktop platform.

Intel's upcoming Meteor Lake processor family is supposedly looking good with the new performance/efficiency targets. According to the @OneRaichu Twitter account, we have a potential performance estimate for the upcoming SKUs. As the latest information notes, Intel's 14th-generation Meteor Lake will feature around a 50% increase in efficiency compared to the 13th-generation Raptor Lake designs. This means that the processor can use half the power at the same performance target at Raptor Lake, increasing efficiency. Of course, the design also offers some performance improvements besides efficiency that are significant and are yet to be shown. The new Redwood Cove P-cores will be combined with the new Crestmont E-cores for maximum performance inside U/P/H configurations with 15-45 Watt power envelopes.

For integrated graphics, the source notes that Meteor Lake offers twice the performance of iGPU found on Raptor Lake designs. Supposedly, Meteor Lake will feature 128 EUs running 2.0+GHz compared to 96 EUs found inside Raptor Lake. The iGPU architecture will switch from Intel Iris to Xe-LPG 'Xe-MTL' family on the 14th gen models, confirming a giant leap in performance that iGPU is supposed to experience. Using the tile-based design, Intel combines the Intel 4 process for the CPU tile and the TSMC 5 nm process for the GPU tile. Intel handles final packaging for additional tuning, and you can see the separation below.

Intel's server processor lineup led by the 4th Gen Xeon Scalable "Sapphire Rapids" processors face stiff competition from AMD 4th Gen EPYC "Genoa" processors that offer significantly higher multi-threaded performance per Watt on account of a higher CPU core-count. The gap is only set to widen, as AMD prepares to launch the "Bergamo" processor for cloud data-centers, with core-counts of up to 128-core/256-thread per socket. A technologically-embattled Intel is preparing quick counters as many as three new server microarchitecture launches over the next 23 months, according to Intel, in its Q4-2022 Financial Results presentation.

The 4th Gen Xeon Scalable "Sapphire Rapids," with a core-count of up to 60-core/120-thread, and various application-specific accelerators, witnessed a quiet launch earlier this month, and is shipping to Intel customers. The company says that it will be joined by the Xeon Scalable "Emerald Rapids" architecture in the second half of 2023; followed by "Granite Rapids" and "Sierra Forest" in 2024. Built on the same LGA4677 package as "Sapphire Rapids," the new "Emerald Rapids" MCM packs up to 64 "Raptor Cove" CPU cores, which support higher clock-speeds, higher memory speeds, and introduce the new Intel Trust Domain Extensions (TDX) instruction-set. The processor retains the 8-channel DDR5 memory interface, but with higher native memory speeds. The chip's main serial interface is a PCI-Express Gen 5 root-complex with 80 lanes. The processor will be built on the last foundry-level refinement of the Intel 7 node (10 nm Enhanced SuperFin); many of these refinements were introduced with the company's 13th Gen Core "Raptor Lake" client processors.

Intel in its Q4-2022 Financial release call reiterated that its Core "Meteor Lake" processor remains on course for a 2H-2023 launch. The company slide does not mention the client form-factor the architecture targets, and there are still rumors of a "Raptor Lake Refresh" desktop processor lineup for 2H, which would mean that "Meteor Lake" will debut as a high-performance mobile processor architecture attempting to dominate the 7 W, 15 W, 28 W, and 35 W device market-segments, with its 6P+16E CPU that introduce IPC increases on both the P-cores and E-cores; and a powerful new iGPU. The slide also mentions that its succeeding "Lunar Lake" architecture is on course for 2024.

"Meteor Lake" is Intel's first chiplet-based MCM processor, in which the key components of the processor are built on various silicon fabrication nodes, based on their need for such a cutting-edge node; such that the cost-optimization upholds the economic aspect of Moore's Law. The compute tile, the die that has the CPU cores, features a 6P+16E setup, with six "Redwood Cove" P-cores, and sixteen "Crestmont" E-cores. At this point it's not known if "Crestmont" cores are arranged in clusters of 4 cores, each. The graphics tile features a powerful iGPU based on the newer Xe-LPG graphics architecture that meets full DirectX 12 Ultimate feature-set. The processor's I/O is expected to support even faster DDR5/LPDDR5 memory speeds, and feature PCIe Gen 5.

Intel's next-generation "Meteor Lake-P" mobile processor with a 6P+8E Compute Tile was shown off at the 2022 IEEE VLSI Symposium on Tech and Circuits (6 performance cores and 8 efficiency cores). We now have annotations for all four tiles, as well as a close-up die-shot of the Compute Tile. Intel also confirmed that the Compute Tile will be built on its homebrew Intel 4 silicon fabrication process, which offers over 20% iso-power performance increase versus the Intel 7 node, through extensive use of EUV lithography.

We had earlier seen a 2P+8E version of the "Meteor Lake" Compute Tile, probably from the "Meteor Lake-U" package. The larger 6P+8E Compute tile features six "Redwood Cove" performance cores, and two "Crestmont" efficiency core clusters, each with four E-cores. Assuming the L3 cache slice per P-core or E-core cluster is 2.5 MB, there has to be 20 MB of L3 cache on the compute tile. Each P-core has 2 MB of dedicated L2 cache, while each of the two E-core clusters shares 4 MB of L2 cache among four E-cores.

Le Comptoir du Hardware scored a die-shot of a 2P+8E core variant of the "Meteor Lake" compute tile, and Locuza annotated it. "Meteor Lake" will be Intel's first processor to implement the company's IDM 2.0 strategy to the fullest. The processor is a multi-chip module of various tiles (chiplets), each with a certain function, sitting on die made on a silicon fabrication node most suitable to that function. Under this strategy, for example, if Intel's chip-designers calculate that the iGPU will be the most power-hungry component on the processor, followed by the CPU cores, the graphics tile will be built on a more advanced process than the compute tile. Intel's "Meteor Lake" and "Arrow Lake" processors will implement chiplets built on the Intel 4, TSMC N3, and Intel 20A fabrication nodes, each with unique power and transistor-density characteristics. Learn more about the "Meteor Lake" MCM in our older article.

The 2P+8E (2 performance cores + 8 efficiency cores) compute tile is one among many variants of compute tiles Intel will develop for the various SKUs making up the next-generation Core mobile processor series. The die is annotated with the two large "Redwood Cove" P-cores and their cache slices taking up about 35% of the die area; and the two "Crestmount" E-core clusters (each with 4 E-cores), and their cache slices, taking up the rest. The two P-cores and two E-core clusters are interconnected by a Ring Bus, and share an L3 cache. The size of each L3 cache slice is either 2.5 MB or 3 MB. At 2.5 MB, the total L3 cache will be 10 MB, and at 3 MB, it will be 12 MB. As with all past generations, the L3 cache is fully accessible by all CPU cores in the compute tile.

Intel is designing a "Halo" SKU of a future generation of mobile processors with a goal to match Apple's in-house silicon of the time. Slated for tape-out some time in 2023, with mass-production expected in 2024, the 15th Generation Core "Arrow Lake-P Halo" processor is being designed specifically to compete with Apple's "premium 14-inch laptop" (presumably the MacBook Pro) that the company could have around 2024, based on an in-house Apple silicon. This is to essentially tell its notebook partners that they will have an SoC capable of making their devices in the class truly competitive. Apple relies on a highly scaled out Arm-based SoC based on in-house IP blocks, with a software that's closely optimized for it. Intel's effort appears to chase down its performance and efficiency.

The Core "Arrow Lake" microarchitecture succeeds the 14th Gen "Meteor Lake." It is a multi-chip module (MCM) of three distinct dies built on different fabrication nodes, in line with the company's IDM 2.0 strategy. These nodes are Intel 4 (comparable to TSMC N7 or N6), Intel 20A (comparable to TSMC N5), and an "external" 3 nm-class node that's just the TSMC N3. The compute tile, or the die which houses the CPU cores, combines a hybrid CPU setup of 6 P-cores, and 8 E-cores. The performance cores are likely successors of the "Redwood Cove" P-cores powering the "Meteor Lake" compute tiles. Intel appears to be using one kind of E-cores across two generations (eg: Gracemont across Alder Lake and Raptor Lake). If this is any indication, Arrow Lake could continue to use "Crestmont" E-cores. Things get interesting with the Graphics tile.

Intel's upcoming "Meteor Lake" and "Arrow Lake" client mobile processors introduce an interesting twist to the chiplet concept. Earlier represented in vague-looking IP blocks, new artistic impressions of the chip put out by Intel shed light on a 3-die approach not unlike the Ryzen "Vermeer" MCM that has up to two CPU core dies (CCDs) talking to a cIOD (client IO die), which handles all the SoC connectivity; Intel's design has one major difference, and that's integrated graphics. Apparently, Intel's MCM uses a GPU die sitting next to the CPU core die, and the I/O (SoC) die. Intel likes to call its chiplets "tiles," and so we'll go with that.

The Graphics tile, CPU tile, and the SoC or I/O tile, are built on three different silicon fabrication process nodes based on the degree of need for the newer process node. The nodes used are Intel 4 (optically 7 nm EUV, but with characteristics of a 5 nm-class node); Intel 20A (characteristics of 2 nm), and external TSMC N3 (3 nm) node. At this point we don't know which tile gets what. From the looks of it, the CPU tile has a hybrid CPU core architecture made up of "Redwood Cove" P-cores, and "Crestmont" E-core clusters.

With its 12th Gen Core "Alder Lake-P" mobile processors still on the horizon, Intel is already building test batches of the 14th Gen "Meteor Lake" mobile processors, at its Fab 42 facility in Chandler, Arizona. "Meteor Lake" is a multi-chip module that leverages Intel's Foveros packaging technology to combine "tiles" (purpose built dies) based on different silicon fabrication processes depending on their function and transistor-density/power requirements. It combines four distinct tiles across a single package—the compute tile, with the CPU cores; the graphics tile with the iGPU: the SoC I/O tile, which handles the processor's platform I/O; and a fourth tile, which is currently unknown. This could be a memory stack with similar functions as the HBM stacks on "Sapphire Rapids," or something entirely different.

The compute tile contains the processor's various CPU core types. The P cores are "Redwood Cove," which are two generations ahead of the current "Golden Cove." If Intel's 12-20% generational IPC uplift cadence holds, we're looking at cores with up to 30% higher IPC than "Golden Cove" (50-60% higher than "Skylake."). "Meteor Lake" also debuts Intel's next-generation E-core, codenamed "Crestmont." The compute tile is rumored to be fabricated on the Intel 4 node (optically a 7 nm-class node, but with characteristics similar to TSMC N5).