TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company's 2024 North America Technology Symposium. TSMC debuted the TSMC A16 technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

This year marks the 30th anniversary of TSMC's North America Technology Symposium, and more than 2,000 attended the event, growing from less than 100 attendees 30 years ago. The North America Technology Symposium in Santa Clara, California kicks off TSMC Technology Symposiums around the world in the coming months. The symposium also features an "Innovation Zone," designed to highlight the technology achievements of our emerging start-up customers.

According to the report from a journal called Fundamental Research, researchers from the Institute of Computing Technology at the Chinese Academy of Sciences have developed a 256-core multi-chiplet processor called Zhejiang Big Chip, with plans to scale up to 1,600 cores by utilizing an entire wafer. As transistor density gains slow, alternatives like multi-chiplet architectures become crucial for continued performance growth. The Zhejiang chip combines 16 chiplets, each holding 16 RISC-V cores, interconnected via network-on-chip. This design can theoretically expand to 100 chiplets and 1,600 cores on an advanced 2.5D packaging interposer. While multi-chiplet is common today, using the whole wafer for one system would match Cerebras' breakthrough approach. Built on 22 nm process technology, the researchers cite exascale supercomputing as an ideal application for massively parallel multi-chiplet architectures.

Careful software optimization is required to balance workloads across the system hierarchy. Integrating near-memory processing and 3D stacking could further optimize efficiency. The paper explores lithography and packaging limits, proposing hierarchical chiplet systems as a flexible path to future computing scale. While yield and cooling challenges need further work, the 256-core foundation demonstrates the potential of modular designs as an alternative to monolithic integration. China's focus mirrors multiple initiatives from American giants like AMD and Intel for data center CPUs. But national semiconductor ambitions add urgency to prove domestically designed solutions can rival foreign innovation. Although performance details are unclear, the rapid progress shows promise in mastering modular chip integration. Combined with improving domestic nodes like the 7 nm one from SMIC, China could easily create a viable Exascale system in-house.

This is likely our last Framework Laptop 16 Deep Dive before we start shipping, and those of you who ordered one can dive deep on your own. We began mass production of Mainboards last week, which we'll hold onto as we resolve the last few remaining open items to begin full system manufacturing. You may be thinking, do we really need a deep dive on connectors? The answer is a resounding "Yes!"—as connectors are surprisingly among the most complex and critical parts of building a product that is slim, durable, high performance, and easy to repair. Connectors are the electrical and mechanical interfaces between modules in the system.

They are what actually makes the product modular! Each connector needs to be easy to engage, hard to accidentally disengage during vibration or drop, robust across repeated re-connections, thin enough to fit within a tiny space, electrically sound from a signal integrity and power perspective, readily manufacturable, and cheap. Our most complicated connectors are made up of dozens of tiny formed metal parts in plastic or metal shells. Given the complexity, our preference is always to find well-proven off-the-shelf connectors. However, occasionally we run into unique interconnect scenarios that don't match anything out there. In these instances, we're forced to customize our own solutions. With Framework Laptop 16, we developed two of these to enable our new module ecosystems.

Zero ASIC, a semiconductor startup, came out of stealth today to announce early access to its one-of-a-kind ChipMaker platform, demonstrating a number of world firsts:

• 3D chiplet composability enabling billions of new silicon products
• Fully automated no-code chiplet-based chip design
• Zero install interactive RTL-based chip emulation
• Roadmap to 100X reduction in chip development costs

"Custom Application Specific Integrated Circuits (ASICs) offer 10-100X cost and energy advantage over commercial off the shelf (COTS) devices, but the enormous development cost makes ASICs non-viable for most applications," said Andreas Olofsson, CEO and founder of Zero ASIC. "To build the next wave of world changing silicon devices, we need to reduce the barrier to ASICs by orders of magnitude. Our mission at Zero ASIC is to make ordering an ASIC as easy as ordering catalog parts from an electronics distributor."

Winbond Electronics Corporation, a leading global supplier of semiconductor memory solutions, has unveiled a powerful enabling technology for affordable Edge AI computing in mainstream use cases. The Company's new customized ultra-bandwidth elements (CUBE) enable memory technology to be optimized for seamless performance running generative AI on hybrid edge/cloud applications.

CUBE enhances the performance of front-end 3D structures such as chip on wafer (CoW) and wafer on wafer (WoW), as well as back-end 2.5D/3D chip on Si-interposer on substrate and fan-out solutions. Designed to meet the growing demands of edge AI computing devices, it is compatible with memory density from 256 Mb to 8 Gb with a single die, and it can also be 3D stacked to enhance bandwidth while reducing data transfer power consumption.

Synopsys, Inc. today announced it is extending its collaboration with TSMC to advance multi-die system designs with a comprehensive solution supporting the latest 3Dblox 2.0 standard and TSMC's 3DFabric technologies. The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance. In addition, Synopsys has achieved first-pass silicon success of its Universal Chiplet Interconnect Express (UCIe) IP on TSMC's leading N3E process for seamless die-to-die connectivity.

"TSMC has been working closely with Synopsys to deliver differentiated solutions that address designers' most complex challenges from early architecture to manufacturing," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Our long history of collaboration with Synopsys benefits our mutual customers with optimized solutions for performance and power efficiency to help them address multi-die system design requirements for high-performance computing, data center, and automotive applications."

Intel recently updated its website to highlight interposers used for testing upcoming chips before their actual product integration. A specific webpage now showcases components used by various tools, notably the "Gen5 VR," which stands for CPU Voltage Regulator in this context. The highlight of the update reveals at least four yet-to-be-announced products: Battlemage (BMG), Arrow Lake (ARL), and Lunar Lake (LNL), slated for launch in 2024. Particularly interesting are the two Battlemage interposers: BGA2362-BMG-X2 and BGA2727-BMG-X3. This hints that a Battlemage GPU could have more pins than Intel's current top-tier GPU from the Alchemist series, known as DG2, which features 2660 pins (BGA2660-DG2-512EU).

This unveiling could indicate Intel's plans to introduce two GPUs in its new series or potentially two different package sizes. Manufacturers often use consistent package sizes for multiple GPUs, granting flexibility to interchange processors with similar specifications and presenting a feasible production strategy. Another notable mention is the Arrow Lake-HX, intended for premium desktop/laptop hybrids.. While there was some buzz about the ARL-HX series before, this update provides clear confirmation from Intel. Lastly, the reveal includes an interposer for the Lunar Lake-M series (LNL-M), which is expected to be Intel's most energy-efficient line. Drawing parallels from the Alder Lake series, such chips were designed for tablets with power consumption between 5 to 7 watts.

Teledyne LeCroy, the worldwide leader in protocol test and measurement solutions, is pleased to announce availability of the OakGate R350-G5-PowerPlus 3U Rackmount Appliance for PCI Express 5.0, with solid state drive (SSD) power and sideband test capabilities.

Data centers and Hyperscalers are measured on their power sustainability and power usage goals and require SSD vendors to test SSD performance during normal system shutdown, abnormal system shutdown, power surges, low and/or idle power states, and voltage fluctuations. SSD vendors would ideally like these test results to highlight competitive product differentiators, often citing lower active power consumption, better power efficiencies and/or reduced cooling efficiencies. SSD design and validation test engineers can now use the OakGate R350-G5-PowerPlus Rackmount Appliance to analyze voltage and current over time and under stress to determine SSD power utilization, efficiency, and consumption, and possibly find opportunities to improve SSD power consumption. Moreover, the R350-G5-PowerPlus operates without the use of 3rd-party power interposers, reducing cost and simplifying test setup.

The Intel Design tools webpage has this week once again provided an early preview of upcoming processors - following on from an LGA1851-MTL-S CPU interposer appearing on the site late last month - indicating that a Meteor Lake-S desktop CPU range was due at some point later in 2023. Intel's latest webpage entry features the "BGA2114-ARL-HX Interposer for the Gen 5 VR Test Tool" with an SKU code that reads: "Q6B2114ARLHX."

The BGA 2114 design points to a mobile processor platform, and industry analysts are fairly certain that Intel is preparing next generation high-end laptop CPUs in the form of its rumored Arrow Lake-HX lineup. This range is set to succeed the 13th generation Core-HX Raptor Lake family of mobile processors. The new BGA package looks to be slightly larger than the closest predecessor, possibly accommodating Intel's new "disaggregated" tile-based (tile is their term for chiplet) internal layout.