Thursday, October 26th 2017
PCI SIG Releases PCI-Express Gen 4.0 Specifications
The Peripheral Component Interconnect (PCI) special interest group (SIG) published the first official specification (version 1.0) of PCI-Express gen 4.0 bus. The specification's previous draft 0.9 was under technical review by members of the SIG. The new generation PCIe comes with double the bandwidth of PCI-Express gen 3.0, reduced latency, lane margining, and I/O virtualization capabilities. With the specification published, one can expect end-user products implementing it. PCI SIG has now turned its attention to the even newer PCI-Express gen 5.0 specification, which will be close to ready by mid-2019.
PCI-Express gen 4.0 comes with 16 GT/s bandwidth per-lane, per-direction, which is double that of gen 3.0. An M.2 NVMe drive implementing it, for example, will have 64 Gbps of interface bandwidth at its disposal. The SIG has also been steered toward lowering the latencies of the interconnect as HPC hardware designers are turning toward alternatives such as NVLink and InfinityFabric, not primarily for the bandwidth, but the lower latency. Lane margining is a new feature that allows hardware to maintain a uniform physical layer signal clarity across multiple PCIe devices connected to a common root complex. This is particularly important when you have multiple pieces of mission-critical hardware (such as RAID HBAs or HPC accelerators), and require uniform performance across them. The new specification also adds new I/O virtualization features that should prove useful in HPC and cloud computing.
PCI-Express gen 4.0 comes with 16 GT/s bandwidth per-lane, per-direction, which is double that of gen 3.0. An M.2 NVMe drive implementing it, for example, will have 64 Gbps of interface bandwidth at its disposal. The SIG has also been steered toward lowering the latencies of the interconnect as HPC hardware designers are turning toward alternatives such as NVLink and InfinityFabric, not primarily for the bandwidth, but the lower latency. Lane margining is a new feature that allows hardware to maintain a uniform physical layer signal clarity across multiple PCIe devices connected to a common root complex. This is particularly important when you have multiple pieces of mission-critical hardware (such as RAID HBAs or HPC accelerators), and require uniform performance across them. The new specification also adds new I/O virtualization features that should prove useful in HPC and cloud computing.
32 Comments on PCI SIG Releases PCI-Express Gen 4.0 Specifications
I know I made typoes. It's vs Its was my favorite. It doesn't mean I didn't try to fix them as fast as I could.
Also you guys shouldn't be so fixated on a typo; the world will continue.
Regarding this gen 4.0, does this mean we can finally have RAID 5 for M.2 SSD drives on non-HEDT platforms? ;)
That might be acceptable for the barely-coherent English-Dutch pidgin that Guru3D's Hilbert excretes, but I've come to expect higher standards from TPU. I don't criticise because it makes me feel better or superior, I criticise because I care about the quality and professionalism of this site's content. And yeah, maybe public shaming isn't the best way to do it, but honestly it should never have happened in the first place.It's vs its is semi-acceptable because a spellchecker won't (and can't) flag that case.
What will be interesting is to see how (and when) Intel and AMD implement this on their CPU and motherboards. I'm expecting Intel to do their standard cheap-assery and offer half the number of lanes they currently do (so instead of 16 lanes of 3.0 from their mainstream CPUs, we'll get 8x 4.0 lanes, although I can hope that they will go with 12 lanes so that M.2 devices aren't bottlenecked through the chipset). I guess it will depend on the actual hardware requirements of PCIe 4.0 i.e. trace thickness.
@Assimilator that burn man, that burn :D Reading the first comment for the news, I was like : ohhh snap :D
It means it current HEDT may live a short life...
Also, to the writers and editors... may I suggest a browser plugin Grammarly. :)
@EarthDog I use Grammarly, and it doesn't pick everything up unfortunately, especially when there's tonnes of html/bbs coding. Spellcheckers in code don't work. :p
For example, that word, tonnes. That's plain English. But not American English. It's actual value is different, even (1.102 short tons US). Do you know how many spell checkers flag that as wrong? Nearly every one. If they can't get THAT right, they can get lots of other things wrong too.
AS to the news, I don't think that this could come soon enough. We need faster drives overall, and SATA just doesn't cut it these days. It would be nice if mechanical drives could be faster, but I don't know if that's even possible. :P
This place needs a gatekeeper BEFORE the news articles are published. Of the many that go up in a day, I would say a few have easily correctable errors which an editor should catch. Many of which Grammarly would catch. Again, it isn't perfect, but it's a lot better than nothing. :)
RE: tonnes/tons, etc.... your EIC needs to pick a writing style and have the team stick to it.
Give them a break, were lucky enough that they post news articles. A few typos isn't the end of the world, seriously. I promise that you won't die.
Just give the guy a break for fk sake! How many foreign languages do you speak btw?? And I mean fluently. Jeeeeez!
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Back on topic, Dave is right. I'm only looking to the PCIE bandwidth for the NVMe SSDs primary.
Seems that, for some reason (overhead), the current PCIE 3.0 x4 lines gets fully saturated on the latest Samsung 960 Pro drives. This can be easily seen when doing a RAID0 with 2 of those drives that caps at ~3.5GB/s for both reads/writes, when already a single drive can do 3.5GB/s for the reads.
Cannot wait for PCIE 4.0 motherboards.
If Prima is talking to me about language, I speak three relatively fluent. Jeez. :p
Perhaps when I am not volunteering as an editor/reviewer for my 7th year at one overclocking site and a paid freelancer at another, I will apply. :)