The complete design was taped out in June 2017, with the first engineering samples of these being tested since last November. Yields are much more complex than just defects, it also comes down to thermals and reliability of various areas of the die. The problem with Intel 10nm is not defects, but getting enough dies which can operate on desired clocks. The launch is delayed because they can't make enough dies of good enough quality to make it profitable, that doesn't mean they have no such dies for testing.
You saw the minimal tweaks AMD did in Zen+, similarly, Intel can do small tweaks in their refinements. Massive delays to Ice Lake will allow Intel to do more of these ahead of release, they are certainly not sitting there doing nothing.
Intel haven't given any performance figures for Ice Lake yet, but if it brings similar cache improvements like Skylake-X/-SP in an even more refined form, that alone can give 3-4%. And if so, Ice Lake will be a larger overhaul than Skylake and Haswell. Overhauls can of course be more or less successful (just look at Bulldozer), but at least it's not a "Skylake 2". I would argue that your estimate of 5% IPC for Ice Lake gains is relatively conservative.
Yeah, you're entirely right that there's obviously something wrong with the power and clock scaling characteristics of Intel's current 10nm dice. I'm interpreting launching an iGPU-less SKU as compensating for defects as well, but of course it's entirely possible that that is also due to power issues (or even something as simple as not wanting to work on launching a driver for an updated GPU arch when there's a single, limited-run SKU out there).
As for me mentioning a 5% IPC increase, I didn't mean that as an estimate at all, I was simply saying that that has been what Intel has managed over their last arch updates (Broadwell and Skylake, at least). Without anything to go by, I'd be expecting anywhere between 5-10% (less would be weird for putting the effort of an arch update into it; more would be the biggest jump in quite a while), but given how long this development cycle has been, I agree that 5% would be unexpectedly low. Still, throwing numbers out like this is at best a guessing game, and purely speculative. Also, I think we're in agreement on the potential for improvements during the delays; nothing ground-breaking (like they probably could have done if they'd been told "hey, you've got two more years to finish this, go nuts!"), but they've definitely had time to iron out bugs and tweak various parameters. You sound right in saying that ES silicon fabbed on a semi-broken process with power/frequency issues can still be used to iron out arhcitecture errata - at least unless those errata only show up at high clocks, which I don't think is very common. Not to mention that power issues probably aren't very problematic in engineering situations, as long as they have a few hefty heatsinks or AIOs lying around.
Btw, have you heard/read anything about whether Intel will be moving to a mesh interconnect with Ice Lake? I don't know if they can match SKL-X's cache hierarchy without one (given the changes in how caches are shared), but from what I've read the mesh comes with a noticeable power penalty. Of course, at least with a 4-core die, there's zero real difference between a mesh and a ring bus
