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Cerebras Updates Wafer Scale Engine on 7 nm - 2.6 Trillion Transistors, 40 GB Onboard SRAM, 850,000 Cores, 12" Wafer

Raevenlord

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Cerebras has announced the successor to their record-breaking Wafer Scale Engine. The newly re-engineered Wafer Scale Engine 2 has been redesigned for TSMC's 7 nm manufacturing process - a severe improvement over the original's 16 nm. That Cerebras has moved on to TSMC's 7 nm for this giant, wafer-sized accelerator is telling of the confidence and state of yields on TSMC's 7 nm - if the process wasn't considered to be stable and guaranteeing incredibly good yields, I doubt such an effort would have been undertaken.






The updated Wafer Scale Engine 2 now packs a staggering 850,000 cores (compared to the original's 400,000); offers 40 GB of on-chip SRAM (up from 18 GB); 20 PetaBytes/s memory bandwidth (up from 9 PB/s), and 220 PB/s interconnect fabric speed (up from 100 PB/s). These improvements and increases have been achieved with the same power envelope as the original, set at a staggering 20 kW (system) and 15 kW (chip) power consumption. These are enabled by the much higher transistor density of 7 nm vs 16 nm, which enables 2.6 Trillion transistors on the Wafer Scale Engine 2 compared to a "paltry" 1.2 Trillion on the original, 16 nm version of it, whilst occupying the same 46,225 square millimeters (about 21.5 x 21.5 cm). Cerebras has one-upped itself, building upon what already had to be the most impressive feat of classical chip engineering.



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Space Lynx

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that is one crazy stock photo with the dining utensils. what ballers. :rockout:
 
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I wonder how they connect it, is it like a sim card for a whole server deck?
 
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Careful now, Raja is carefully watching you, he's seeing potential to finally rival Nvidia chips.

Die size is after all just a detail.
 

hat

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I heard about this before, but I still have no idea what these are being used for, or by who.
 
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Reminds me, it's time for dinner.... :D
 
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I always love the idea of this, but they never have details on things like how they're going to package it (surely it's not just this naked slab - as sweet visually as that would be) and also things like thermals when you light up an entire silicon wafer at once.

That said, still love the idea.
 
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that is one crazy stock photo with the dining utensils. what ballers. :rockout:
I bet that was entirely aimed at DR. Ian Cutress.
 
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Happy now? :laugh:
1619038841057.png
 
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need 4 of this to eat on them lol

i didn't found in their white papers how to clean them after
 
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if the process wasn't considered to be stable and guaranteeing incredibly good yields, I doubt such an effort would have been undertaken
I think you wouldnt care that much about yields when you can sell single sheet system for million or more.
I mean, it costs like 50USD or so to print chips on single wafer, so even with 5% yield rate you would only need 20 wafers before you get the perfect one. Thats only a kilo of USD. Selling that perfect wafer for a million covers production costs for decades.
 
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I think you wouldnt care that much about yields when you can sell single sheet system for million or more.
I mean, it costs like 50USD or so to print chips on single wafer, so even with 5% yield rate you would only need 20 wafers before you get the perfect one. Thats only a kilo of USD. Selling that perfect wafer for a million covers production costs for decades.
Somewhere there was an article about the cost of the wafers. 7nm wafer cost $ 10k there. The design itself allows you to bypass problem areas. So, at this cost of the wafer, I think you are generally right about the latter statement.
 

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15kw ... I wonder how efficient this chip is, compared to the conventional ones.
 
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