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| System Name | RBMK-1000 |
|---|---|
| Processor | AMD Ryzen 7 5700G |
| Motherboard | ASUS ROG Strix B450-E Gaming |
| Cooling | DeepCool Gammax L240 V2 |
| Memory | 2x 8GB G.Skill Sniper X |
| Video Card(s) | Palit GeForce RTX 2080 SUPER GameRock |
| Storage | Western Digital Black NVMe 512GB |
| Display(s) | BenQ 1440p 60 Hz 27-inch |
| Case | Corsair Carbide 100R |
| Audio Device(s) | ASUS SupremeFX S1220A |
| Power Supply | Cooler Master MWE Gold 650W |
| Mouse | ASUS ROG Strix Impact |
| Keyboard | Gamdias Hermes E2 |
| Software | Windows 11 Pro |
AMD already declared the CPU core counts of its EPYC "Genoa" and "Bergamo" processors to top out at 96 and 128, respectively, a core-count believed to have been facilitated by the larger fiberglass substrate of the next-gen SP5 CPU socket, letting AMD add more 8-core "Zen 4" chiplets, dubbed CPU complex dies (CCDs). Until now, AMD has used the chiplet as a common component between its EPYC enterprise and Ryzen desktop processors, to differentiate CPU core counts.
A fascinating theory that hit the rumor-mill, indicates that the company might leverage 5 nm (TSMC N5) carve out larger CCDs with up to 16 "Zen 4" CPU cores. Half of these cores are capped at a much lower power budget, essentially making them efficient-cores. This is a concept AMD appears to be carrying over from its 15-Watt class mobile processors, which see the CPU cores operate under an aggressive power-management. These cores still turn out a reasonable amount of performance, and are functionally identical to the ones on 105 W desktop processors with a relaxed power budget.
Since the "fat" and "slim" cores are functionally identical to each other; AMD need not develop a complex middleware like the Intel Thread Director, and can make do with OS scheduler-level optimizations that it can co-develop with Microsoft or the Linux community, much like it did for older versions of the "Zen" microarchitecture that featured multiple CCXs.
The theory also predicts that AMD might build on the 3D Vertical Cache technology. The next-gen CCD might feature two layers, the bottom layer with CPU cores and their dedicated L2 caches; and a top layer exclusively for a 64 MB 3D Vertical Cache serving as a shared L3 cache. In the "Zen 3" 3DV Cache CCD, the 64 MB SRAM is located above the region of the CCD that typically has its 32 MB L3 cache, a relatively cooler component than the CPU cores. On the new CCD, this SRAM could be located over the region that has the low-TDP cores, pushing the high-TDP "performance" cores to the periphery of the die, with structural silicon conducting heat from these cores to the surface.
This theory is way out there, but it's plausible because AMD doesn't have a formidable low-power CPU core architecture to rival "Gracemont." and because Intel's next-gen "Raptor Lake" chips are rumored to see the addition of more E-core clusters, making the "i9-13900K" a 24-core processor, beating AMD in the core-count game. If we were to nitpick, we'd point out that the low-TDP cores take as much valuable die real-estate and transistor-count as the high-TDP cores; and die-size (i.e. wafer volumes) are a rather scarce resource these days. We'll find out in the second half of 2022.
Many thanks to TheoneandonlyMrK for the tip
View at TechPowerUp Main Site
A fascinating theory that hit the rumor-mill, indicates that the company might leverage 5 nm (TSMC N5) carve out larger CCDs with up to 16 "Zen 4" CPU cores. Half of these cores are capped at a much lower power budget, essentially making them efficient-cores. This is a concept AMD appears to be carrying over from its 15-Watt class mobile processors, which see the CPU cores operate under an aggressive power-management. These cores still turn out a reasonable amount of performance, and are functionally identical to the ones on 105 W desktop processors with a relaxed power budget.
Since the "fat" and "slim" cores are functionally identical to each other; AMD need not develop a complex middleware like the Intel Thread Director, and can make do with OS scheduler-level optimizations that it can co-develop with Microsoft or the Linux community, much like it did for older versions of the "Zen" microarchitecture that featured multiple CCXs.
The theory also predicts that AMD might build on the 3D Vertical Cache technology. The next-gen CCD might feature two layers, the bottom layer with CPU cores and their dedicated L2 caches; and a top layer exclusively for a 64 MB 3D Vertical Cache serving as a shared L3 cache. In the "Zen 3" 3DV Cache CCD, the 64 MB SRAM is located above the region of the CCD that typically has its 32 MB L3 cache, a relatively cooler component than the CPU cores. On the new CCD, this SRAM could be located over the region that has the low-TDP cores, pushing the high-TDP "performance" cores to the periphery of the die, with structural silicon conducting heat from these cores to the surface.
This theory is way out there, but it's plausible because AMD doesn't have a formidable low-power CPU core architecture to rival "Gracemont." and because Intel's next-gen "Raptor Lake" chips are rumored to see the addition of more E-core clusters, making the "i9-13900K" a 24-core processor, beating AMD in the core-count game. If we were to nitpick, we'd point out that the low-TDP cores take as much valuable die real-estate and transistor-count as the high-TDP cores; and die-size (i.e. wafer volumes) are a rather scarce resource these days. We'll find out in the second half of 2022.
Many thanks to TheoneandonlyMrK for the tip
View at TechPowerUp Main Site
