They should do a whole range of X3D processors so even people like myself without £500 for a chip can enjoy extending the life of there platform.
Apparently, that's what AMD planned to do but there must have been some "last-minute" problems, due to which they released a 5800X3D only.
The pictures which show that 5800X3D when delided has interposers in place just confirms that AMD aimed at 2-chiplet 3DV Zen3/Vermeer+ CPU models...
It's sort of odd as the 5800X3D isn't really better than the 5800. It's better in gaming, it's at best on par with the it and very often worse by a good margin in content creation.
This isn't completely true. There are some workloads, like some compression algorithms (data, not A/V) or databases which benefit hugely from the large cache...
Also, there will definitely be some scientific calculations, simulations, etc. which do not require server-type processors, like EPYC's which woudl nevertheless benefit from a large cache.
They just downclock to the point the CPU is stable at max 1.35V as it is right now with the 5800X3D. Basicly your getting a 16 core 32 thread but 99.9% with a lower clockspeed.
The problem is the DRAM that is responsible for the additional cache cant cope with voltages higher then 1.35V. It's still connected to the CPU voltage in terms. So as long as they dont design a seperate voltage rail for the DRAM cache, we cant overvolt or really push the chips to it's limits.
SRAM, not DRAM. CPU cache is SRAM (static RAM)...
But I agree otherwise what with you are saying...
I just think that R9X3D wasn't worth it when Zen4 is just around the corner.
So they would release 5950X3D now? That doesn't make any sense.
Clearly they encountered a specific "last-minute" problem, that's why they have released 5800X3D only initally.
That AMD wants to release 5900X3D or 5950X3D now shows, that the 3DV-cache actually is much more important in terms of future roadmap/innovations than just simply increasing the cache size.
As it seems, a 3DV-cache will allow AMD to free the CPU chiplet off the L3 cache completely which will make place for "little cores" (aka Zen 4c) to be added to the CPU chiplet. This way AMD will be able to double the number of cores (albeit with a half of "small cores") on the AM5 platform. Using more 3D-stacked chiplets, it will have the possibility to have even more cores without having to have a yet another platform...
It's suicide to release more 3Ds or Zen 4 or anything for the AM4 platform while the AM5 is due to be released in a couple of months.
The only reason of doing something like that, is probably the current economic situation globally.
No, the only reason of doing that is that AMD desperately needs a 2-chiplet CPU with 3DV-cache to be tested "in the wild" as soon as possible.
Which means that AMD will be using the 3DV-stacked L3 cache for other purposes than just increasing the cache amount and it will be really soon (otherwise AMD could have waited for Raphael with the 3DV-cache).
There are some rumours about Raphael-X being released in the end of this year. That means that a 3DV-stacked L3 is a part of what Raphael-X will be, but it isn't the only fancy technology, Raphael-X will bring.
Most probably, the 3DV-cache will be used to free the CPU chiplet off the L3 cache so that they can add "little" core (Zen 4c) into the CPU chiplet.
And AMD apparently doesn't want to make too many steps at once so they need to test the 3DV-cache alone with 2 CPU chiplets.
That's why they are willing to risk that 5950X3D will bring less interests in the AM5 platform initially, because they have to do this (Raphael-X) right as they need more cores to be able to compete against Raptor Lake and Meteor Lake...
The AM5 platform will have X3D parts out this year too!
Most probably, Raphael-X will depend heavily on the 3DV-technology, but that will allow to do a much more fancy stuff than just having more L3 cache...
It will create internal competition - why does AMD insist to produce two lineups with approximately equal or similar performance characteristics?
Zen 3 3D =~ Zen 4.
Because they need the 3DV-technology in order to bring a big.little architecture with 2x the core count to compete against Raptor Lake/Meteor Lake.
They need that the 3DV-cache technology is tested thoroughly also with 2-chiplets / CPU before they can make further steps.