Seems like the 3D cache was much more beneficial with DDR4. DDR5 almost doubles the bandwidth with similar latency, so the gains are much smaller.
But even moreso than that, Zen 4 is a quite bit faster than Zen 3, and this is primarily achieved through front-end improvements, which ultimately means it will be less cache sensitive. So we should expect it to get smaller gains from extra L3 cache (relatively speaking).
There are still cases where the additional cache helps tremendously. F1 2021 and Watch Dogs Legion see enormous gains.
Yes, those are edge cases. Cherry-picking edge cases to prove a point isn't a particular good argument, especially if you want to extrapolate this into general performance. The F1 game series have been known to be outliers for years, and I find it interesting that they don't even use the latest game in the series.
Keep in mind that CPUs aren't like GPUs; they are latency engines, i.e. designed to reduce the latency of a task. For them, latency trumps bandwidth, and L3 cache's latency advantage is even greater for Zen 4 because of Zen 4's higher clocks.
Firstly, L3 doesn't work the way most people think;
L3 (in current AMD and Intel architectures) is a spillover cache for L2, you should
not think of it like a
faster piece of RAM or a
little slower L2. L3 will only be beneficial when you get cache hits there, and unlike L2, you don't get cache hits there from prefetched blocks etc. as L3
only contains recently discarded blocks from L2. L3 is a LRU type cache, which means every cache line fetched into L2 will push out another from L3.
You get a hit in L3 when: (ordered by likelyhood)
- An instruction cache line has been discarded from this core (or another core).
- A data cache line has been discarded from this core, most likely due to branch misprediction.
- A data cache line has been discarded from another core, but this is exceedingly rare compared to the other cases, as data stays in L3 for a very short time, and the chances of multiple threads accessing the same data cache line within a few thousand clock cycles is minuscule.
This is the reason why we see only a handful applications be sensitive to L3, as it has mostly to do with instruction cache. For those who know low level optimization, the reason should be immediately clear; highly optimized code is commonly known to be less sensitive to instruction cache, which essentially means better code is less sensitive to L3. Don't get me wrong, extra cache is good. But don't assume software should be designed to "scale with L3 cache", when that's a symptom of bad code.
Secondly, regarding latency vs. bandwidth;
Latency is always better when you look at a single instruction or a single block of data, but when looking at real world performance you have to look at the overall latency and throughput. If for instance a thread is stalled and waiting for two or more cache lines to be fetched, then slightly higher latency doesn't matter as much as bandwidth. This essentially comes down to the balance between data and how often the pipeline stalls. More bandwidth also means the prefetcher can fetch more data in time, so it might prevent some stalls all together. This is why CPUs overall are much faster than 20 years ago, even though latencies in general have gradually increased.
But this doesn't really apply to L3 though, as the L3 cache works very differently as described above.
Lastly, when compared to a small generational uplift, like Zen 2 -> Zen 3 or Zen 3 -> Zen 4, the gains from extra L3 is pretty small and the large gains are mostly down to very specific applications. This is why I keep calling it mostly a gimmick. If you on the other hand use one of those applications where you get a 30-40% boost, then my all means go ahead an buy one, but for everyone else, it's mostly something to brag about.
Intel 13900K official supported memory is DDR5 5600 :
https://www.intel.com/content/www/u...-36m-cache-up-to-5-80-ghz/specifications.html everything above that is based on your luck at silicon lottery.
Not to mention that you are likely to downgrade that speed over time (or risk system stability).