AMD 5th Gen EPYC "Turin" Pictured: Who Needs Accelerators When You Have 192 Cores?

[btarunr]

AMD's upcoming server processor, the 5th Gen EPYC "Turin," has been pictured as an engineering sample is probably being evaluated by the company's data-center or cloud customers. The processor has a mammoth core-count of 192-core/384-thread in its high-density cloud-focused variant that uses "Zen 5c" CPU cores. Its regular version that uses larger "Zen 5" cores that can sustain higher clock speeds, also comes with a fairly high core-count of 128-core/256-thread, up from the 96-core/192-thread of the "Zen 4" based EPYC "Genoa."

The EPYC "Turin" server processor based on "Zen 5" comes with an updated sIOD (server I/O die), surrounded by as many as 16 CCDs (CPU complex dies). AMD is expected to build these CCDs on the TSMC N4P foundry node, which is a more advanced version of the TSMC N4 node the company currently uses for its "Phoenix" client processors, and the TSMC N5 node it uses for its "Zen 4" CCD. TSMC claims that the N4P node offers an up to 22% improvement in power efficiency over N5, as well as a 6% increase in transistor density. Each of the "Zen 5" CCDs is confirmed to have 8 CPU cores sharing 32 MB L3 cache memory. A total of 16 such CCDs add up to the processor's 128-core/256-thread number. The high-density "Turin" meant for cloud data-centers, is a whole different beast.



The "Turin" processor uses 12 "Zen 5c" CCDs. Much like "Zen 4c" is to "Zen 4," the "Zen 5c" is a physically compacted version of the larger "Zen 5" core that has the same ISA (instruction sets) and IPC, but typically runs at lower clock speeds than the regular "Zen 5" cores. It's meant for high core-count processors. The high-density "Turin" MCM has the same sIOD as the regular "Turin," but with 12 "Zen 5c" CCDs. Each CCD has 16 "Zen 5c" cores share a 32 MB L3 cache. This is interesting—if you recall, the current "Zen 4c" CCD has two CCX (CPU core complexes) that each has 8 "Zen 4c" cores share a 16 MB L3 cache. The "Zen 5c" CCD doubles the total addressable L3 cache.

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[TumbleGeorge]

is expected to build these CCDs on the TSMC N4P foundry node

Hmm what about rumours for "3"nm? I think that in next few months will have some capacity free of Apple.

 

[R0H1T]

At some point they need to rationalize these codenames ~ Rome, Bergamo, Naples, Turin, Phoenix(2) et al, way too many of them

 

[tabascosauz]

Hmm what about rumours for "3"nm? I think that in next few months will have some capacity free of Apple.

Nobody will use N3 (original), it's a shit experiment that only Apple signed up for, and will be dead node as soon as Apple stops using it. All other N3 customers will start on N3E or N3P, which are just starting production. So there's no "freed up capacity".

Nobody will be using N3 for this product either b/c they will pay $$$$ out the ass for all these CCDs. Neither do they need N3's characteristics - server clocks low, dense core probably even lower. At least until N3E/N3P becomes a mature, affordable node (like N6 was last year, like N5 was this year, like N4 is becoming now).

 

[Crackong]

1x Zen5c CCD + V-cache = possible Best gaming CPU 2025 ?

 

[TumbleGeorge]

Nobody will use N3 (original), it's a shit experiment that only Apple signed up for, and will be dead node as soon as Apple stops using it. All other N3 customers will start on N3E or N3P, which are just starting production. So there's no "freed up capacity".

Nobody will be using N3 for this product either b/c they will pay $$$$ out the ass for all these CCDs. Neither do they need N3's characteristics - server clocks low, dense core probably even lower. At least until N3E/N3P becomes a mature, affordable node (like N6 was last year, like N5 was this year, like N4 is becoming now).

That's clear and fair enough, but I didn't write 3N in my comment. Free capacity means that there will be pipeline space and does not indicate the node version that would be used. Little has been written about it. There are a number of companies listed that will use the capacity freed up by Apple, and AMD is one of those companies.

 

[btarunr]

1x Zen5c CCD + V-cache = possible Best gaming CPU 2025 ?

The problem with "c" cores is not cache, but lower Vcore limits. So it can't clock high enough.

 

[Crackong]

The problem with "c" cores is not cache, but lower Vcore limits. So it can't clock high enough.

Isn't that a perfect match with V-cache?
They've locked the vcore in all Zen4 V-cache SKUs anyway.

 

[dj-electric]

Isn't that a perfect match with V-cache?
They've locked the vcore in all Zen4 V-cache SKUs anyway.

Zen4c's frequency capability takes a nosedive over typically high frequencies according to AMD. Those high frequencies aren't the 5Ghz+ you're used to seeing on current X3D chips, but much much lower to the point where using 3DVC might send the effective frequency into a height so low that it will risk the validity of using this technology in the first place.

Maybe AMD could overcome this limitation with future core designs, who knows.

 

[Vayra86]

At some point they need to rationalize these codenames ~ Rome, Bergamo, Naples, Turin, Phoenix(2) et al, way too many of them

Seems simple:
Italy

 

[Mathragh]

Isn't that a perfect match with V-cache?
They've locked the vcore in all Zen4 V-cache SKUs anyway.

regarding V-cache: afaik one of the ways they shrunk the 4c chiplets is not including the vias for the extra cache. This was for zen4c so maybe things are different for zen5c, but i'm not sure.
The reasoning can go both ways, but I expect they don't focus on cache too much for those compact cores since they also already have half the L3 cache per core.

 

[Denver]

Seems simple:
Italy

Yeap, AMD has good taste. Certainly much better than random lakes.

Interestingly, only the Zen5c will be produced at 3nm, probably because the cache no longer shrinks with new processes.

 

[Daven]

My ideal Zen 5 desktop:

Zen 5 CCD - 8 (16) cores, 6+ GHz clocks, 15+% IPC

Zen 5c CCD - 16 (32) cores, 5+ GHx clocks, 15+% IPC, 128 MB 3D V cache

Total cores (threads): 24 (48)

Zen 5 IOD - major memory controller improvements (DDR6400+ without going into a lower gear), native USB4, RDNA4 with 4 CUs

 

[N/A]

N3P in server 2025. mainstream GPU/CPU by 2026.. N3 only suitable for mobile

Hmm what about rumours for "3"nm? I think that in next few months will have some capacity free of Apple.

 

[zlobby]

At some point they need to rationalize these codenames ~ Rome, Bergamo, Naples, Turin, Phoenix(2) et al, way too many of them

Like intel ones are better.

 

[Count von Schwalbe]

Like intel ones are better.

IDK, I rather enjoyed the thought of Coffee Lake and Whiskey Lake. Raptor Lake seemed kind of dangerous (maybe Cannon Lake could fix that?), though, and Ice Lake is way too cold for me.

I am curious as to the performance and efficiency of these compared to the Ampere Altra AmpereOne 192-core ARM-based CPU.

 

[R0H1T]

maybe Cannon Lake could fix that?

How? Do you prefer gunpowder over mineral oil

 

[Count von Schwalbe]

Jurassic Park would have been a lot shorter if they all had cannons...

 

[zlobby]

IDK, I rather enjoyed the thought of Coffee Lake and Whiskey Lake. Raptor Lake seemed kind of dangerous (maybe Cannon Lake could fix that?), though, and Ice Lake is way too cold for me.

I am curious as to the performance and efficiency of these compared to the Ampere Altra AmpereOne 192-core ARM-based CPU.

Only thing worse than intel's naming is nvidia's. Mofos think they are free to use famous people's names for their own gains!
Even worse, they think their products are worthy of bearing the said names!

How? Do you prefer gunpowder over mineral oil

In all honesty, your question (albeit humorous) sounds a lot like 'We have no butter…but I ask you—would you rather have butter or guns?' to me.

 

[Count von Schwalbe]

Only thing worse than intel's naming is nvidia's. Mofos think they are free to use famous people's names for their own gains!
Even worse, they think their products are worthy of bearing the said names!

I apologise if I wasn't clear - this is what I was referring to.

 

[Denver]

I apologise if I wasn't clear - this is what I was referring to.
View attachment 325905View attachment 325906View attachment 325908View attachment 325909View attachment 325911

Apparently all of these lakes really exist in the USA. I don't even want to know why it's called Whiskey Lake

 

[Count von Schwalbe]

Apparently all of these lakes really exist in the USA. I don't even want to know why it's called Whiskey Lake

I can't tell for sure, but I suspect it is a shortened version of Whiskeytown Lake in California. Which was named for the town of Whiskeytown, a mining town that was submerged to make the lake.

 

[zlobby]

I apologise if I wasn't clear - this is what I was referring to.
View attachment 325905View attachment 325906View attachment 325908View attachment 325909View attachment 325911

Oh, that part was clear. I don't stand corrected, though.

 

[Tek-Check]

Mighty powerful, indeed!

The high-density "Turin" MCM has the same sIOD as the regular "Turin," but with 12 "Zen 5c" CCDs. Each CCD has 16 "Zen 5c" cores share a 32 MB L3 cache. This is interesting—if you recall, the current "Zen 4c" CCD has two CCX (CPU core complexes) that each has 8 "Zen 4c" cores share a 16 MB L3 cache. The "Zen 5c" CCD doubles the total addressable L3 cache.

And Turin dense should be arriving on N3 derivative.

Hmm what about rumours for "3"nm? I think that in next few months will have some capacity free of Apple.

Turin Dense is on N3 derivative.

Nobody will be using N3 for this product either b/c they will pay $$$$ out the ass for all these CCDs. Neither do they need N3's characteristics - server clocks low, dense core probably even lower. At least until N3E/N3P becomes a mature, affordable node (like N6 was last year, like N5 was this year, like N4 is becoming now).

Turin Dense should be on one of those two N3 derivatives.

At some point they need to rationalize these codenames ~ Rome, Bergamo, Naples, Turin, Phoenix(2) et al, way too many of them

You have Italian cities for server chips. What is difficult here?

1x Zen5c CCD + V-cache = possible Best gaming CPU 2025 ?

No.

Maybe AMD could overcome this limitation with future core designs, who knows.

They are testing hybrid solution with Phoenix2 APU. This might scale up in future.

 

[tabascosauz]

And Turin dense should be arriving on N3 derivative.
Turin Dense is on N3 derivative.
Turin Dense should be on one of those two N3 derivatives.

Where? Aside from a dozen vague old claims echoing the same leak that "AMD will use N3 and N4 for Zen 5".

Probably doesn't align with known N3P schedule, but if Zen 5 debuts in middle of 2024 then I guess it makes sense for N3E maturity/adoption.