I think it's yields, the c clusters are very tiny even with 16 of them in there. Also to fit 192 of them in an Epyc socket probably needs 3mn for size reasons but i'll have to look at Turin again to check if 4nm would've worked.
They've already done zen4c at 5nm, whereas the current AM5 IO die is fabbed on 6nm.
At 5nm the 4c core is 2.5mm², which if they just optically enlarged it (yeah I know, they probably wouldn't just do that) would be roughly 3mm², which is very roughly the same size as one of the infinity fabric logic blocks (GMI3 PHY) - they could probably optimise this very easily. So loose one of the GMI3 blocks and replace it with 1 zen4c core and add another 3 zen4c cores along the top edge.
In theory you end up with a hybrid IO die roughly 10% bigger than the 125mm² normal one. If they really engineered it they could probably make it only a few percent bigger as I'm sure there's extra logic that could easily rearrange.
Obviously the biggest issue would be controlling heat, etc., but they could lock the max clocks of the 4c cores to something non-offensive.
End result: Ryzen 3 base CPU... add a salvaged 4 or 6 core CCD and you could have an enhanced Ryzen 5 lineup and start knocking that ball game of thread counts Intel is pushing using P+E thread counts back into Intel's court seeing as the zen4c cores still do hyper threading whereas the 'E' cores don't... oh and still do AVX-512 (if anybody cares).
Side note: It's crazy to think a whole general purpose CPU core is actually smaller than the VCN or DCN blocks...