Inside cIOD the infinity fabric writes/reads 32 Bytes / cycle (256bits/cycle) to the Unified Memory Controller which in turns writes/reads at most 128 bits / cycles in dual memory channel to the RAM.
If everything runs at 1:1:1, how is it possible to write/read 256 bits / cycle to RAM which is only 128 bits / cycle at most in dual memory channel ?
If everything runs at 1:1:1, how is it possible to write/read 256 bits / cycle to RAM which is only 128 bits / cycle at most in dual memory channel ?
The big Ryzen 7000 Memory and OC Tuning Guide - Infinity Fabric, EXPO, Dual-Rank, Samsung and Hynix DDR5 in Practice test with Benchmarks and Recommendations | igor´sLAB
AMD’s new Ryzen 7000 desktop CPUs, based on the Zen4 micro-architecture, still use the same chiplet design as their predecessors, with a few small but not negligible changes. Igor already gave details…
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