Zen 6 will have GMI links with enough bandwidth to not starve 12 cores, so it makes logical sense to have 2 GMI links for 24 full fat cores.
Each CCD will have two GMI links on die, but in desktop space one of them has been in use so far, to connect each CCD to IOD. If named 'GMI4', it should support speeds close to PCIe 6.0 because Venice EPYC has been leaked to introduce this interface.
Currently, one GMI3 link, a tad above PCIe 5.0 speed, supports theoretical maximum of 72 GB/s (16x36Gbps/8).
For Zen6, one GMI4 link, close to PCIe 6.0 speed, should support theoretical minimum of 128 GB/s (16x64Gbps/8).
They may have the IPC and efficiency advantage over Intel, but they're really behind in terms of core counts.
They are not "behind" because 16 cores provide overall higher performance in applications on 9950X than 24 cores on 285K. Also, 8 core 9800X3D is significantly faster in gaming than 24 core 285K. So, it's nonsense to say that they are "behind" in core count. It's not about core count.
Increasing core count to 24 on Zen6 will give 48 threads. They seem confident enough that this would be sufficient to counter alleged 52 single threaded cores on Nova Lake.