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Intel 10A (1 nm-class) Node to Enter Mass Production in 2027

Daven said:
From the TPU article in the link above:

“According to a China Times news article: "Gelsinger also confirmed the expansion of orders to TSMC, confirming that TSMC will hold orders for Intel's Arrow and Lunar Lake CPU, GPU, and NPU chips this year, and will produce them using the N3B process.”

“Past leaks have indicated that Intel's Arrow Lake processor family will have CPU tiles based on their in-house 20A process, while TSMC takes care of the GPU tile aspect with their 3 nm N3 process node.”
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Simple. Some are on 20A and some are on N3.
Kipicog said:
Intels 20A factory in germany should be up and running, I guess we will see if Arrow Lake will use 20A or not later this year, might be Intel 4
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Nothing outside of Meteorlake and the Ericsson SoC is, will be Intel 4. Arrowlake will be 20A and N3 for compute tile.
lexluthermiester said:
They are not abandoning their existing fabs. They have to use TSMC while they upgrade/rebuild some them to spead out their workload.
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Someone actually using their brain. The whole in-house-or-nothing mentality is hurtful in the short term when they are trying to make sure neither the process team nor the design team gets hampered by delays of each other.
 
DavidC1 said:
Someone actually using their brain. The whole in-house-or-nothing mentality is hurtful in the short term when they are trying to make sure neither the process team nor the design team gets hampered by delays of each other.
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It's also about capacity planning. How many processors are we planning to sell in each quarter of 2025 and 2026? What will our fab capacity be in each quarter? Not enough, just enough or too much?
 
DavidC1 said:
Simple. Some are on 20A and some are on N3.

Nothing outside of Meteorlake and the Ericsson SoC is, will be Intel 4. Arrowlake will be 20A and N3 for compute tile.

Someone actually using their brain. The whole in-house-or-nothing mentality is hurtful in the short term when they are trying to make sure neither the process team nor the design team gets hampered by delays of each other.
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Wirko said:
It's also about capacity planning. How many processors are we planning to sell in each quarter of 2025 and 2026? What will our fab capacity be in each quarter? Not enough, just enough or too much?
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Exactly. Intel is not stupid. They're taking advantage of a third party fab so they can upgrade and rebuild their own fabs. Not just good planning but very smart.
 
Daven said:
Someone posted a good youtube video explaining this a few days ago.

Edit: here it is

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That's by far the most annoying video and voice from all Youtube and Internets. Sorry, but was torture to hear her for more than 30 secs.
 
Prima.Vera said:
Sorry, but was torture to hear her for more than 30 secs.
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I hadn't watched it yet. You are not wrong. She's as cute as can be, but that voice.. I would go insane in the membrane if subjected to that for more than a few minutes.. Can you imagine if she was a screamer? I would never want to get busy again.. Or would laugh my ass off..
 
Makes sense since n+1 and n+2 are probably used for GPU and SOC tiles and n+3 for CPU tiles. once built factories need to co-exist to recoup the investment and get the most value out of them.
 
MxPhenom 216 said:
Intel will be using the same lithography for sub Intel 7 geometries as TSMC has been using for their 3-7nm. They are not as far behind as you think. Lithography is the technology (ie EUV) used for patterning step of fabricating. Transitioning to EUV is basically mandatory to keep improving density. All major fabs have basically moved to EUV for sub 7nm geos.

For the record, Intel 7 has a smaller fin pitch than TSMC 7 even though its channel length (where traditionally transistors get their sizes) is longer. Intel 7 is also comparable in density as TSMC 7 because the fin pitch is less. Kind of why they call it Intel 7. It used to be their Superfin 10, but recent improvements too it makes it their 7. Its just kind of bad perf/watt.

Basically, saying something is Xnm doesnt mean shit these days due to transistor structures being very different than they used to be and largely marketting now. Transistors can be the same size from say TSMC 7 to TSMC 6, but to make it TSMC 6 they just say its density is improved, perf/watt is better, area better but transistors themselves didnt change. There could even be another flavor of cell that has different VT characteristics added to the library.
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I undersanding that but they are still 5 years behind, we need HEDT parts with Intel 4 lithography or newer to catch up. Zen 5 is rumored to be on TSMC 3N. Intel performance per watt is appalling right now.
 
phints said:
I undersanding that but they are still 5 years behind, we need HEDT parts with Intel 4 lithography or newer to catch up. Zen 5 is rumored to be on TSMC 3N. Intel performance per watt is appalling right now.
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They arent 5 years behind tho....

And if you dont let boards unload as much power as they want to the CPU that the CPU does not need, their perf/watt isnt actually that bad.
 
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phints said:
I undersanding that but they are still 5 years behind, we need HEDT parts with Intel 4 lithography or newer to catch up. Zen 5 is rumored to be on TSMC 3N. Intel performance per watt is appalling right now.
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LOL. Intel has already taped out Clearwater Forest on 18A. I'm no Intel fanboy, all AMD products for me, but Intel is clearly progressing rapidly on their process nodes and is rapidly catching up to TSMC. This is great news as TSMC needs a healthy kick up the arse. Hopefully serial over-hyper and under-deliverer Scamsung can get their shit together with 2nm as well. Having 3 major players would be good news for the global chip market and consumers.
 
phints said:
I undersanding that but they are still 5 years behind, we need HEDT parts with Intel 4 lithography or newer to catch up. Zen 5 is rumored to be on TSMC 3N. Intel performance per watt is appalling right now.
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They are not 5 years behind. Sierra Forest is coming in less than 3 months using Intel 3. Whatever site you are reading from they are wrong.
 
lexluthermiester said:
Um...

...hmmm.

I am not getting into that pedantic debate..
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It's not being pedantic - it is objective reality. The marketing claims made by companies regarding their transistor lithography are pointless, and it's pointless to directly compare them by name alone because no feature on the transistor actually matches that value - even if it matches some other transistor, like a planar transistor at some size(1nm referenced here in the article for Intel 10A), not every company is going to use the same method of arriving at the conclusion for their name.

So again, comparing transistor lithographies between companies is totally pointless.

Even looking at Intel 10A, it's obvious that most of the time, they're moving the decimal over. So Intel 20A is likely a "2nm-class" transistor lithography.
 
DavidC1 said:
They are not 5 years behind. Sierra Forest is coming in less than 3 months using Intel 3. Whatever site you are reading from they are wrong.
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Nothing I said is wrong, the current Intel HEDT CPUs are 5 years behind. They are still on Intel 7 process and that's why AMD leads them by 3x the performance per watt in some cases with 7900X and 7800X3D. They need to release Intel 4 lithography based HEDT CPUs asap, their new fab is MIA once again.
 
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