AMD Ryzen 7 9800X3D Has the CCD on Top of the 3D V-cache Die, Not Under it

[Ferrum Master]

Great, now time to give some resources to the BIOS development so it doesnt look so half baked, as the hardware is sound so far. And it would be pretty if they put the NeoGeo boot music when the system shows the BIOS logo

I want it as soothing as PS2 boot was.

 

[FreedomEclipse]

It's Ɛᗡ Ʌ-cache now, if actually true.

does it cache from the silicon down under?

 

[igormp]

Well, well well! Consider me very excited for the future of AM5 now.

If this really works as well as it sounds, they might as well discontinue the non-X3D line going forward.

If they can manage to make the price difference negligible, then fully agree.
Otherwise I would prefer to not pay extra for some useless feature (for me, just to be clear).

 

[trsttte]

A different possibility OP didn't consider is designing smaller chips with no L3 at all and then just stacking them on top of L3 cache dies. One of the changes between Zen4/4c and Zen5/5c was halving the L3 cache, now imagine they drop a cache tile under it to compensate for that.

The only obstacle is really intel not putting forward competing products to entice this, luckily the increasing market share from Apple and the threat from Qualcomm and Windows on ARM will keep them motivated.

 

[adilazimdegilx]

This made sense to me at first but I'm not sure about the feasibility of it after seeing 9700x's die shots for two reasons. First, L2 cache area is quite a bit smaller than before hence L3 cache would be harder to lineup on top or bottom (they can't use longer interconnections to reach further due to latency). Secondly, number of interconnection points between L3 and chip are reduced a lot in 9700x die photos which should limit the bandwidth of the cache unless they came up with something smarter.

For these reasons I think they might be planning something even crazier. They might be able tackle both of these problems by putting L3 cache on both sides!

This way they'd have enough area for same sized L3 and since they can connect it from both sides number of interconnections doubles which solves the bandwidth problem.

This wouldn't help with the IHS and core contact problem but it shouldnt be much of a deal this time around. 105w power limit and cores with larger die area (larger than 7000 series) it should perform at least as good as 9700x in multicore scenarios by default anyway. This would also explain why AMD wanted a 65w 9700x. Now their 3D chip wouldn't look slower in any scenario compared to non 3d counterpart (except maybe single core).

Edit: This setup would also help to increase the L3 cache. 128MB would be a stretch but 96MB should be pretty possible.

 

[RimbowFish]

and why not to add another 64MB ON TOP too

 

[izy]

and why not to add another 64MB ON TOP too

Cost and technical complexity probably + maybe some games / apps wont benefit too much with more cache to the point that it makes sense to add more.

 

[TumbleGeorge]

But when 3D V cache will become really 3D?

 

[izy]

But when 3D V cache will become really 3D?

Look at it with 3D glasses

 

[N/A]

Great. now on A16 flip it again because of backside power delivery.

 

[eidairaman1]

Well, well well! Consider me very excited for the future of AM5 now.

If this really works as well as it sounds, they might as well discontinue the non-X3D line going forward.

If it helps in non gaming scenarios and meshes with even faster ram.

 

[Dr. Dro]

Wouldn't the CCD be even higher (close to the cooler because of the thinner lid) than standard non X3D CCD? So even better temperatures than the regular Ryzens

Temperature probably wouldn't be much better, but it'd definitely bring the dissipation closer to the level achieved by regular chips. Sounds trivial, but this a really complicated advance in CoWoS. These are looking more and more appealing by the minute

 

[Makaveli]

Temperature probably wouldn't be much better

X3D cache models don't have high temps to begin with.

 

[remekra]

9900X3D and 9950X3D will be interesting. Seems they can now put the 3D Vcache under both chiplets.

 

[mb194dc]

I have a bad feeling that anything launched this year is going to be screwed!!

Probably more likely that the increase at 1440p and above which comprises pretty much all use cases, even with with a 4090 will be minimal.

 

[ZoneDymo]

9900X3D and 9950X3D will be interesting. Seems they can now put the 3D Vcache under both chiplets.

^ this, the 9800X3D will probably be a minimal upgrade over the 7800X3D but those two might be sweet.

 

[mkppo]

Damn, I was hoping they'll double stack the cache since the L3 area in Zen 5 is too small for an extra 64MB cache to be stack on top of the L3 on the die. So theoretically they could double stack two 24MB L3 dies for some extra cache. But it would probably result in even greater thermal issues.

This alleviates that IU suppose but there's no extra cache

9900X3D and 9950X3D will be interesting. Seems they can now put the 3D Vcache under both chiplets.

Economically not viable especially considering the performance uplift will be minimal

 

[kondamin]

Oh and for Zen 6 they'll do shingled caches and Zen 7 will have the caches Pendicular

Fabric trough memory might become a thing though

 

[Wirko]

Temperature probably wouldn't be much better, but it'd definitely bring the dissipation closer to the level achieved by regular chips. Sounds trivial, but this a really complicated advance in CoWoS. These are looking more and more appealing by the minute

Stacked dies are also thinned down, I think AMD or TSMC said to 50 µm, so both together are the same thickness as one non-stacked die (CCD or IOD). If stacking increases thermal resistance, it's not because of thickness, it's because of the "glue".

Oh and for Zen 6 they'll do shingled caches and Zen 7 will have the caches Pendicular

Don't give them ideas, or else we'll have to put up with QLC processors one day soon! It wouldn't even be a first!

 

[Makaveli]

Economically not viable especially considering the performance uplift will be minimal

V-cache on both CCD's also doesn't address Dual CCD traffic latency. I also think there will be gains but minimal.

 

[Eternit]

Why don't they do 2D cache like in RDNA3?

 

[droid99]

so ryzen 9 9000 could have an 3D v-cache on both CCD chiplets?

 

[kondamin]

V-cache on both CCD's also doesn't address Dual CCD traffic latency. I also think there will be gains but minimal.

As branch prediction becomes better that latency becomes less relevant and since Zen 5's main upgrade was just that...

Why don't they do 2D cache like in RDNA3?

AM5 is to small for that
Well the socket might still be OK but the PCB is to small

 

[claylomax]

I think this would cost more than normal x3d to manufacture

Exactly; and it's going to launch with no competition.

 

[TumbleGeorge]

Why don't they do 2D cache like in RDNA3?

It is still flat.