AMD Ryzen 7 9800X3D Has the CCD on Top of the 3D V-cache Die, Not Under it

[Vayra86]

Amazing

Interesting.

Fabulous.

 

[Steevo]

Fabulous.

Darling

 

[TechLurker]

AM5 is to small for that
Well the socket might still be OK but the PCB is to small

Just move Ryzen to the underutilized Threadripper socket then. More space for more cache, a bigger iGPU, more I/O, and a bigger heatspreader for more cooling. Problem solved. Just move some M2 slots to under the motherboard and closer to the CPU. /humor

 

[BatRastard]

I think having the 3dVcache cache below was the way to go from the start, the limitation were pretty annoying with it on top but we have to see the results first, im still hopping for a a 12 core single die CPU with 3dvchase in the future, that would be amazing.

I agree, but I speculate that a major concern then was with compression with the heatsinks despite the heat spreader and support structure to protect everything. Protect the cores at the cost of the stacked cache chiplet getting crushed ...

 

[yfn_ratchet]

Interesting idea, but I'm still cagey about it. If a lot of the improvements on Zen 5 X3D is just due to higher power targets it's losing what I like about the X3D chips in the first place, and that is amazing gaming performance at low-ish power. If it's about the same as the 7800X3D I'm just gonna get the 7800X3D, lest they whoopsie a new IOD on these with more gen 5 lanes and CKD support.

 

[mama]

Now all they need to do is make the 9900X3D relevant by putting vcache on both CCDs!

 

[eMWu]

Well, in theory this can be a good move.
1. Much easier to cool the cores
2. This let AMD to increase the clock speed
3. They could use bigger cache chip/size?
4. That may make it easier to provide the 3D cache to all CCDs

 

[TumbleGeorge]

AMD Ryzen 7 9800X3D appears in first content creation benchmarks with GeForce RTX 4090 - VideoCardz.com

AMD Ryzen 7 9800X3D The upcoming 8-core CPU was spotted PugetBench. AMD soon-to-be-released X3D processor has debuted on PugetBench, a content-creator oriented benchmark suite. The exact source of this test is unclear, but it is either an early sample now being tested by motherboard vendors...

videocardz.com

I don't know how to categorise this, leak or rumour. But results seems good.

 

[InVasMani]

I mentioned this type of design seeming to be more ideal eon's ago to do with chip dies and cache stacking. It makes sense from a thermals perspective plus with the cache on bottom you have a lot more potential to simply make it thicker and insert more cache. This is how I envisioned it looking all along honestly from a design standpoint.

Another thing they could do with this is place their different CCD ZenCore types above or below the higher performant ZenCore type though it impacts the trace lengths a bit to the stacked cache below. Lastly they could put the higher performing ZenCore CCD above the stacked cache and lower performing, but more efficient ZenCore CCD below the stacked cache. That last option eliminates the trace lengths concern, but might be less ideal on thermals overall though probably better balanced to keep thermals of the higher performing ZenCore CCD higher. The bottom CCD would really just be there for efficiency and additional cores for higher multi-thread performance where needed.

I don't see them doing that right off, but if their trying to push things in the direction of 16c32t it's likely what they'll be considering.

 

[Carillon]

What if for zen6 they make the cache die a bit longer, so that a small area can slip under the IOD?

 

[Raiden85]

Always found the X3D versions to run a bit warmer due to that cache, so hopefully this might bring the temps back down a bit.

My 5800XD ran quite a bit warmer than my 5950X in games by a good 15°C to 20°C, and this was on a 360mm AIO, and my 7950X3D actually runs cooler in games than the 5800X3D did but still warmer than the 5950X did.

 

[SL2]

This would hypothetically make way for a single 128 MB V-cache chip under both CCD's.

There'are probably loads of things that makes this hard or complicated, but I have no idea if this is impossible.

On the other hand, what's taking so long with 9900X3D/9950X3D? Isn't it pretty much the same thing as last time? Maybe there's more difference between the generations than moving the cache after all?

 

[Godrilla]

^ this, the 9800X3D will probably be a minimal upgrade over the 7800X3D but those two might be sweet.

I care mostly about the 0.1% lows, even with a 8% delta overall gain let's face it these will sell out instantly from the looks of things. Things that will contribute to this will be R9s launching later, Arrow Lake and Raptor lake cluster fudging simultaneously. 7800X3D EOL. I feel bad for those who sell their hardware prematurely without replacement hoping to purchase one on day one. Cheers!

 

[InVasMani]

This would hypothetically make way for a single 128 MB V-cache chip under both CCD's.

There'are probably loads of things that makes this hard or complicated, but I have no idea if this is impossible.

On the other hand, what's taking so long with 9900X3D/9950X3D? Isn't it pretty much the same thing as last time? Maybe there's more difference between the generations than moving the cache after all?

Beyond that it potentially allow for 256MB of cache could be leveraged by one out of the two CCD's or slit partitioning out the available cache.

 

[SL2]

I simply meant a single set of V-cache available directly to all cores on both CCD's. That would also make higher core count CCD's less needed, for now.

256 MB sounds like diminishing returns to me.

 

[demirael]

Wouldn't this increase latency? Or is going through TSV negligible latency-wise?
I guess the higher clockspeed could make up for it?

Why would it increase latency? The vias should be no different in length and there isn't any more logic on the path.

This made sense to me at first but I'm not sure about the feasibility of it after seeing 9700x's die shots for two reasons. First, L2 cache area is quite a bit smaller than before hence L3 cache would be harder to lineup on top or bottom (they can't use longer interconnections to reach further due to latency).

Latency? Light travels .3 meters in 1 ns. Latency isn't an issue.

 

[InVasMani]

I simply meant a single set of V-cache available directly to all cores on both CCD's. That would also make higher core count CCD's less needed, for now.

256 MB sounds like diminishing returns to me.

I probably got the cache mixed up anyway, but yeah 256MB would probably generally be diminishing returns for now at least. Everything kind of changes with progress and time though. As other technology matures maybe that looks different in terms of usefulness. I just meant being able to divvy out the available stacked cache between both CCD's seems like a positive if they can do so and also control how it's done between the two CCD's. You don't necessary need or want both CCD's to use a equal distribution of available cache. You might want to reserve more for one and less for the other for a given usage scenario.

The only way it might impact latency negatively is stacking a CCD on top of another CCD on top of X3D cache the top CCD in that scenario would have a bit longer trace lengths to the cache though it would be better located in terms of heat output. That theoretical would still be better than the current 7950X3D with the CCX latency issues though.

 

[user556]

Fabulous.

Darling

Absolutely

 

[evernessince]

Economically not viable especially considering the performance uplift will be minimal

Hard disagree, AMD has X3D cache in chips all the way down to the 5600X3D.

Having 2 cache chiplets on $700 - $750 parts is likewise absolutely possible.

Even if the uplift is a mere 3%, every little bit matters at the high end. Particularly when it could make the 9950X3D reach gaming parity with the 9800X3D, it would upsell a lot of people to the more expensive processor.

 

[SL2]

You don't necessary need or want both CCD's to use a equal distribution of available cache. You might want to reserve more for one and less for the other for a given usage scenario.

I don't think that's needed with cache size is this large, and all cores are connected to all cache anyway. I'm talking ONE SINGLE V-cache chip for ALL cores.

The only way it might impact latency negatively is stacking a CCD on top of another CCD on top of X3D cache the top CCD in that scenario would have a bit longer trace lengths to the cache though it would be better located in terms of heat output.

I haven't heards about such a thing, sounds like a really bad idea. AMD just moved V-cache in order to cool the CCD properly, that would one step forward, three steps backwards.

 

[SOAREVERSOR]

Hard disagree, AMD has X3D cache in chips all the way down to the 5600X3D.

Having 2 cache chiplets on $700 - $750 parts is likewise absolutely possible.

Even if the uplift is a mere 3%, every little bit matters at the high end. Particularly when it could make the 9950X3D reach gaming parity with the 9800X3D, it would upsell a lot of people to the more expensive processor.

Most of the people buying high core count chips aren't doing it for gaming and the X3D chips perform worse in most productivity and creative tasks where high core count matters. X3D makes much more sense for six and eight core chips than 16 core chips.

 

[SL2]

Most of the people buying high core count chips aren't doing it for gaming

The 7950X3D isn't for most people and AMD knows it. You can dig up any sales number if you don't believe me.

and the X3D chips perform worse in most productivity and creative tasks where high core count matters.

Not because of added cache, tho. Big difference.

 

[Oberon]

Solutions that were obvious after the introduction of the first X3D parts; just needed to wait for the design to catch up.

 

[SOAREVERSOR]

The 7950X3D isn't for most people and AMD knows it. You can dig up any sales number if you don't believe me.

Not because of added cache, tho. Big difference.

Yes because of the added cache. The added cache produces gains in some areas but the limits it imposes causes losses in other areas. There's nothing wrong with that. It's great tech it's got a very specific focus and trade offs such as this have always existed. It's a lateral move to focus on a specific area.

 

[SL2]

Yes because of the added cache.

Nope.

It's the slower clock speed that causes lower performance.