AMD Ryzen 7 9800X3D Has the CCD on Top of the 3D V-cache Die, Not Under it

[evernessince]

I read it and it's really not hard to understand the article but the part about not losing clocks is pure speculation. Turns out they were incorrect anyway and looking at the boost clocks between 9700x and 9800X3D, there's still a hit to clocks albeit less than before.

1) That's a different leak, not a fact as you seem to be implying

2) You are assuming that the 9800X3D will be clocked as high as the 9950X3D. If they can increase the clocks on the new X3D, they may choose to further segment by having higher clocks on the higher end part.

Mind you either way the frequency is increasing as compared to prior gen X3D parts so relative to past X3D parts any performance different as a result of the X3D cache will have changed this generation.

So yeah, adding L3 to both CCD's would reduce productivity for a minor gain in performance. What's worse is that it'll increase performance for unwanted situations which they would want to mitigate through drivers anyway because ideally you want the gaming cores to be pinned to one CCD. In situations where it jumps to another, it won't match the 9800X3D's performance simply because of the latency incurred to jump to the other CCD.

So you're looking at a slight benefit for games in edge cases and a slight hit to productivity for a CPU that costs more. Pretty sure AMD said the same during 7950X3D launch when they did the math. Whether that changes remains to be seen

Ok now I understand. You read the article, you just don't know what you are talking about / can't understand it.

"slight benefit for games in edge cases"?

Clearly you are unaware that the 7950X3D was 14% faster on average than the 7950X in games.

Even if there were 0 frequency improvements to the 9950X3D, it would mirror that performance increase at the very least.

In the CPU world that isn't slight, it's what you typically get with a new architecture.

You also don't seem to understand what edge cases are either, X3D's boost is not only to edge cases. A wide array of games benefit from X3D. You seem to be arguing against X3D in general which is just dumb. Every benchmark out there disproves you.

Also, since when is an increase in performance "unwanted"? Utter nonsense.

 

[mkppo]

1) That's a different leak, not a fact as you seem to be implying

2) You are assuming that the 9800X3D will be clocked as high as the 9950X3D. If they can increase the clocks on the new X3D, they may choose to further segment by having higher clocks on the higher end part.



Ok now I understand. You read the article, you just don't know what you are talking about / can't understand it.

"slight benefit for games in edge cases"?

Clearly you are unaware that the 7950X3D was 14% faster on average than the 7950X in games.

Even if there were 0 frequency improvements to the 9950X3D, it would mirror that performance increase at the very least.

In the CPU world that isn't slight, it's what you typically get with a new architecture.

You also don't seem to understand what edge cases are either, X3D's boost is not only to edge cases. A wide array of games benefit from X3D. You seem to be arguing against X3D in general which is just dumb. Every benchmark out there disproves you.

Also, since when is an increase in performance "unwanted"? Utter nonsense.

I'm not sure what's with the aggression and finger pointing here. I'm not even trying to argue with you, just having a discussion and you are misunderstanding what I am trying to say and instead blaming that I don't understand the article. I know full well what X3D means and what it does to games. Here I was trying to decipher what effect the larger L1 and changes to L2 and TLB registers would mean for added L3 and here you are trying to imply I don't understand a basic article rife with speculation. Anyway..

So here's where you're mistaken in understanding what i'm trying to say. When AMD released the 7950X3D, they specifically instructed everyone to use the game bar and X3D chipset drivers. I'm sure you know the reason why - it was to pin cores used by a game to a single CCD with V-Cache. The reason is simple - when threads fly to the other CCD there's a significant latency penalty which hurts performance. This was made to be a huge deal but in my own experience with the 7950X3D, it wasn't much of an issue with the games I play as games were always constrained to one CCD.

Now when it come to having V-Cache on both CCD's, it will only increase performance in cases where gaming threads fly from one CCD to the other (as the L3 on the, or supposedly under the CCD, isn't shared by the other CCD). These are cases which AMD wants to minimise anyway - the best case scenario is where all gaming threads are pinned to one CCD. Thankfully, those are edge cases as most games stay pinned to one CCD anyway. That's basically what I meant by edge cases - i'm not arguing that having X3D doesn't increase performance by 15% or so in games. We are talking about having X3D on both CCD's which as I mentioned will only increase performance in those non-so-ideal and thankfully rare cases where threads are flying around.

So if, hypothetically, the 7950X3D had a 8% performance deficit vs 7800X3D in those specific games where games aren't constrained to one CCD, it will maybe reduce to 3%? It won't be zero, as you will always incur the CCD hopping latency. The end result is you will have a slight performance hit to productivity (provided there's a clockspeed penalty), and gaming performance won't match up to the 7800X3D but it'll be closer for sure.

Regarding the leaks, we can agree to disagree. I think there will be a clockspeed regression again, but less so than before. If you believe there won't be any then sure, it makes some sense to put X3D's on both dies because you'll gain performance in those edge cases while sacrificing none for productivity. Whether that is the case remains to be seen but i'm skeptical.

 

[InVasMani]

Nope.

It's the slower clock speed that causes lower performance.

That's still because of the designing of added cache of X3D. At least the changes should resolve that issue. I think honestly AMD should just sandwich a CCD above and below the X3D cache if they need more cores and performance eventually. It's pretty much the best means they can go about it currently. Also could in theory insert more more X3D cache above or below those CCD's. There are obviously positives and negatives to thermals and scaling associated with that whole approach, but like NAND and HBM layers they can just keep stacking them in that manner with that approach.

I wonder if maybe we'll get a bottom CCD that's lower power and below that like a stacked L1 or L2 cache for that chip or something to essentially use it as a accelerated low power high I/O multi-threaded chip? Like it doesn't need to be just last level cache so who knows if they could stack things at different power stages in intended usage scenario's in a effective practical manner. Perhaps they'll slap a NPU chip under the stacked cache. Placing iGPU under would make some sense and maybe have it's own X3D underneath it. They could probably make it reversible too so if you want to sell a chip more as a APU flip it over for better thermals and frequency scaling of the iGPU portion of the design.

Being able to flip and reverse a CPU design for a more targeted design emphasis would be rather cool and flexible. From a manufacturing standpoint with defects it also would make sense. Like if they did place a CCD on top and bottom they can just put the CCD that lab tests better on top and solder it down with the CDD binning that scaled worse on the bottom.

 

[SL2]

That's still because of the designing of added cache of X3D.

You set a 7950X and a 7950X3D both to the same Hz and you'll see. The cache does not cause losses in any significant way.

 

[InVasMani]

You set a 7950X and a 7950X3D both to the same Hz and you'll see. The cache does not cause losses in any significant way.

Thermals due to how the cache was designed it has nothing to do with IPC.

 

[RUSerious]

I wonder if maybe we'll get a bottom CCD that's lower power and below that like a stacked L1 or L2 cache for that chip or something to essentially use it as a accelerated low power high I/O multi-threaded chip? Like it doesn't need to be just last level cache so who knows if they could stack things at different power stages in intended usage scenario's in a effective practical manner. Perhaps they'll slap a NPU chip under the stacked cache. Placing iGPU under would make some sense and maybe have it's own X3D underneath it. They could probably make it reversible too so if you want to sell a chip more as a APU flip it over for better thermals and frequency scaling of the iGPU portion of the design.

It's not going to happen that way. If anything, AMD will add more chiplets and move off the standard organic substrate to pack them more tightly like Intel is doing. Power consumption for interconnects decreases (pJ/bit) and interconnect data rates increase. I don't think AMD will ever significantly beef up the iGPU on Ryzen's IOD, so no need for extra cache there. AMD laptop/compact desktop SoCs have all the graphics power needed for typical business and home use. dGPUs are added for gaming. Vertical stacking (the 3D) will always be a problem in terms of thermals. We are not talking .75kW HPC/AI accelerators here. The various experiments with liquid or vapor change cooling 'tunnels' in the silicon structure are not for desktop CPUs. Too many $$$s.

 

[Squared]

Thermals due to how the cache was designed it has nothing to do with IPC.

IPC is instructions per clock cycle. X3D allows some applications including many games to complete more instructions per cycle. But X3D on top of the CPU dies has so far resulted in cooling problems that necessitate a lower frequency clock, resulting in a net loss for applications that don't see higher IPC from more cache.

 

[InVasMani]

IPC is instructions per clock cycle. X3D allows some applications including many games to complete more instructions per cycle. But X3D on top of the CPU dies has so far resulted in cooling problems that necessitate a lower frequency clock, resulting in a net loss for applications that don't see higher IPC from more cache.

I was saying thermals are why frequency were lower. AMD originally designed the X3D cache a particular way and it limited frequency. They've revised it and corrected the design for good reason.

 

[RUSerious]

I was saying thermals are why frequency were lower. AMD originally designed the X3D cache a particular way and it limited frequency. They've revised it and corrected the design for good reason.

Yeah, but you are just stuck in a loop over being pedantic. I don't think the rest of us are enjoying this so much. Maybe just but it to rest - IMHO.

 

[SL2]

Thermals due to how the cache was designed it has nothing to do with IPC.

I never said IPC, but it's a way to test if V-cache is hampering performance, which it won't.

I was saying thermals are why frequency were lower.

No, you didn't from the beginning and you know it, otherwise I'd never reply.

 

[DemonicRyzen666]

This would hypothetically make way for a single 128 MB V-cache chip under both CCD's.

There'are probably loads of things that makes this hard or complicated, but I have no idea if this is impossible.

On the other hand, what's taking so long with 9900X3D/9950X3D? Isn't it pretty much the same thing as last time? Maybe there's more difference between the generations than moving the cache after all?

the CCD's are thicker in Zen 5 the 3D-cache die is also much bigger than all other versions now, there's also a connection layers between multiple dies thats why it's thicker. but this also means the dies are now even closer to the IHS for better cooling.