AMD Curve Optimizer any guides / experience

[Ibizadr]

In corecycler I'm with original config only change time in each core but I see in some posts related to corecycler the creator attend to test it first with small fft to give more boost in light thread to the cores and it gives errors more frequently. In original config it uses huge fft, what the best way to to some tests with small or huge ffts?

 

[tabascosauz]

In corecycler I'm with original config only change time in each core but I see in some posts related to corecycler the creator attend to test it first with small fft to give more boost in light thread to the cores and it gives errors more frequently. In original config it uses huge fft, what the best way to to some tests with small or huge ffts?

Small FFT should reduce clocks - in P95 the bigger the FFT size the more it goes into memory/memory controller and you'll often see lower temps and higher clocks. But in reality, testing between Small FFT, Large FFT and Huge FFT, there's not much of a difference in clocks...................as long as you don't enable AVX. So stay on SSE like default.

If you have the time (it's easier for you because you only have 8 cores), you could just test All FFTs like I do. But that takes much longer and you have to extend the time period significantly to cover all FFT sizes in that range - I run just over an hour.

More importantly is that you let it run for at least 3 iterations on every core (I let it cycle overnight through at least 5 iterations). Once you're on the edge, often an unstable core will pass one or two iterations, seemingly stable, only to fail on the next one - so if you only let it run for one or two cycles, you might assume that it was "stable" when it actually wasn't.

 

[Taraquin]

In corecycler I'm with original config only change time in each core but I see in some posts related to corecycler the creator attend to test it first with small fft to give more boost in light thread to the cores and it gives errors more frequently. In original config it uses huge fft, what the best way to to some tests with small or huge ffts?

I run it at default setting and used event viewer to find the last slghtly unstable core. I would start with - 30 on all and +200 pbo, if negative is way of you get error quick, if it's slightly iff it fails after a few minutes or in test 2.

 

[Ibizadr]

When pc reboots when doing corecycle I need to lower the value on the core that reboot my pc? Like to 21 to 19?

 

[Taraquin]

When pc reboots when doing corecycle I need to lower the value on the core that reboot my pc? Like to 21 to 19?

Yes, try that. Do you see ehich core it worked on when reboot occured? Only lower that one.

 

[Ibizadr]

Yes, try that. Do you see ehich core it worked on when reboot occured? Only lower that one.

I check in event viewer and on log created in corecycle, it's the same core on event viewer and corecycler last core tested so I assumed that core need more voltage

I have my cpu llc on auto in my msi b450 tomahawk max II, it's better to put it in mode 4 like 1usmus advice in CTR 2.1or leave it on auto?

 

[tabascosauz]

I check in event viewer and on log created in corecycle, it's the same core on event viewer and corecycler last core tested so I assumed that core need more voltage

I have my cpu llc on auto in my msi b450 tomahawk max II, it's better to put it in mode 4 like 1usmus advice in CTR 2.1or leave it on auto?

The recommendation in CTR is because CTR either wants you to use a static all-core OC according to its recommendation, or use its own hybrid OC mechanism (half of which is still basically static all-core).

Messing around in CO is still under PBO, which is still just stock boost. When on PB stock boost, leave it on auto, because iirc droopy and loose LLC is actually what the boost algorithm wants. Aggressive LLC can make static OC easier, but for stock boost aggressive LLC doesn't help/doesn't change anything/hurts boost.

 

[Ferrum Master]

The recommendation in CTR is because CTR either wants you to use a static all-core OC according to its recommendation, or use its own hybrid OC mechanism (half of which is still basically static all-core).

Messing around in CO is still under PBO, which is still just stock boost. When on PB stock boost, leave it on auto, because iirc droopy and loose LLC is actually what the boost algorithm wants. Aggressive LLC can make static OC easier, but for stock boost aggressive LLC doesn't help/doesn't change anything/hurts boost.

I was supporting CRT on the Patreon. Well it turned out ugly. CTR is an ugly mess, I will not ever recommend it to anyone, not mentioning the fact the coder is a whining bitch, his emails for supporters were like from a demanding ex and he didn't realize that his bug driven tool is really so much full of shit it is barely usable to ask money for it and blaming anyone having problems with it, it ain't the tool, but you. Very unprofessional.

Well it all depends on your sample and motherboard... it very wild setting wise as far I experienced. The LLC does react different in between vendors, it is normal as VRMS differ a lot and their speed and performance.

In the end it is just experiment. Example for my 5950X.

1. Make your RAM solid stable.
2. Do not touch anything CPU voltage wise, adjust the RAM domain and VSOC, CCD, IOD voltages depending on your RAM amount(like how many sticks) gen and speed. It is very crucial not to overdo there, but leaving it stock is not an also an option often. Depends on the board. AUTO often gives worst results.
3. PBO. I do it the old fashioned way, in a notebook(I mean the one having paper). I wrote down my core statistics. I have two CCD's, each two best core pairs, then second then third. So I gradate them. Best for may CCX0 have -2m then second best pair has -6. Then other -16. For Second CCX I have the same except the best have -4 then next pair -10 and then -16 for other.
4. Then do Power limit play depending if you wish more multicore or single core performance. Yes, that's decided there.

Any suggestions for my maybe flawed reasoning?

 

[outpt]

when looking for the correct core to adjust go to event viewer log for the processor APIC ID:#. this tells you what core crashed. Go back into CPUZ and look at tool and save report as text. you can save this to desktop if you want to.
some times core numbering can start as core-0 or core-1. CPU-Z helps making sure you are adjusting the correct core.

 

[Ibizadr]

I was supporting CRT on the Patreon. Well it turned out ugly. CTR is an ugly mess, I will not ever recommend it to anyone, not mentioning the fact the coder is a whining bitch, his emails for supporters were like from a demanding ex and he didn't realize that his bug driven tool is really so much full of shit it is barely usable to ask money for it and blaming anyone having problems with it, it ain't the tool, but you. Very unprofessional.

Well it all depends on your sample and motherboard... it very wild setting wise as far I experienced. The LLC does react different in between vendors, it is normal as VRMS differ a lot and their speed and performance.

In the end it is just experiment. Example for my 5950X.

1. Make your RAM solid stable.
2. Do not touch anything CPU voltage wise, adjust the RAM domain and VSOC, CCD, IOD voltages depending on your RAM amount(like how many sticks) gen and speed. It is very crucial not to overdo there, but leaving it stock is not an also an option often. Depends on the board. AUTO often gives worst results.
3. PBO. I do it the old fashioned way, in a notebook(I mean the one having paper). I wrote down my core statistics. I have two CCD's, each two best core pairs, then second then third. So I gradate them. Best for may CCX0 have -2m then second best pair has -6. Then other -16. For Second CCX I have the same except the best have -4 then next pair -10 and then -16 for other.
4. Then do Power limit play depending if you wish more multicore or single core performance. Yes, that's decided there.

Any suggestions for my maybe flawed reasoning?

I don't touch in my ram for now only load xmp. My advise is too run corecycler it's a really useful tool to do the work for CO. I never experienced an error in corecycler only reboots but I think my best cores was a bit high negative (-18,-14) if you don't got errors or reboots try again but edit config file and add more time per core and try to do it at least 3 iteration. For example I pass 3 iterations of 6min per core yesterday and today try 15min per core and it reboots. So always give a second try to corecycler with more time per core.

when looking for the correct core to adjust go to event viewer log for the processor APIC ID:#. this tells you what core crashed. Go back into CPUZ and look at tool and save report as text. you can save this to desktop if you want to.
some times core numbering can start as core-0 or core-1. CPU-Z helps making sure you are adjusting the correct core.

Yes in event viewer appears APIC ID and i think after its the thread number dont know this way to know the numbering via cpu z. Thanks for that tip I use corecycler log to see what core corresponding to APIC ID error

 

[Ferrum Master]

I don't touch in my ram for now only load xmp. My advise is too run corecycler it's a really useful tool to do the work for CO. I never experienced an error in corecycler only reboots but I think my best cores was a bit high negative (-18,-14) if you don't got errors or reboots try again but edit config file and add more time per core and try to do it at least 3 iteration. For example I pass 3 iterations of 6min per core yesterday and today try 15min per core and it reboots. So always give a second try to corecycler with more time per core.


Yes in event viewer appears APIC ID and i think after its the thread number dont know this way to know the numbering via cpu z. Thanks for that tip I use corecycler log to see what core corresponding to APIC ID error

XMP is not a thing you can trust on. It is often made for intel platforms, it does not work on AMD the same.

Corecyler is for those random reboots on standby. The real prime test or any relatives is for all core stability. For gaming test I use some Final Fantasy benches, I have them found good triggering random BSODS on CPU instability as those are not very GPU dependent.

3 iterations is not enough... I leave usually each test of my config overnight.

 

[AVATARAT]

I don't like anymore corecycler because it's overvolting cores.
Now I prefer OCCT with the following settings:

Just run this core by core and lower or upper the Curve optimizer on the core that gets an error.
But be careful because sometimes too much or too lower voltage on one core can affect the other core next to it.
Normally you can get an error in 20-30 seconds.

 

[Ibizadr]

I don't like anymore corecycler because it's overvolting cores.
Now I prefer OCCT with the following settings:

View attachment 220056 View attachment 220057

Just run this core by core and lower or upper the Curve optimizer on the core that gets an error.
But be careful because sometimes too much or too lower voltage on one core can affect the other core next to it.
Normally you can get an error in 20-30 seconds.

From my experience in the last days I think you are right when you say sometimes voltage on one core affect other core next to it. I will give a try with occt and your settings too since it gives errors more faster than corecycler in your words.

 

[mrthanhnguyen]

Anyone know why I can do linpack extreme but fail to run geekbench 5. What is the cause?

 

[Mussels]

Anyone know why I can do linpack extreme but fail to run geekbench 5. What is the cause?

They load the hardware different.

Just means linpack isn't exposing your instability.

 

[AVATARAT]

Anyone know why I can do linpack extreme but fail to run geekbench 5. What is the cause?

Because your CPU goes to a higher clock where the voltage is not enough for one or a few cores, probably the fastest cores.

 

[jesdals]

New AMD chipset driver out

 

[freeagent]

Do people install those? What do they actually do that the windows drivers don’t?

 

[jesdals]

Do people install those? What do they actually do that the windows drivers don’t?

Mess up your curve settings

 

[Deleted member 202104]

Do people install those? What do they actually do that the windows drivers don’t?

The latest one does this:

Strangely, it's only listed when you choose the X570 chipset on the driver page, but the release notes say it's for B550 as well.

 

[outpt]

dl for my b550 and installed . No problems. Will test

 

[Mussels]

L3 Cache results went from ~625 to ~655
Driver good.

 

[Nordic]

Do people install those? What do they actually do that the windows drivers don’t?

They actually have a very strong impact on performance. It made a huge difference back when ryzen 3000 first came out. This driver will probably be really important for windows 11.

 

[Mussels]

Do people install those? What do they actually do that the windows drivers don’t?

For zen 1/2, they add a ryzen power plan that helps performance out.

For Zen 3, they add these sort of performance fixes. They also include chipset, USB drivers, sata, etc etc - minor fixes and such that you dont really notice.

 

[RJARRRPCGP]

linpack isn't exposing your instability.

That is common, if there's bus instability. (Usually CPU-to-bus communication issues, most likely CPU-bus termination issues)

I had that with a poopy Core 2 Quad Q6600 G0 at only 367 Mhz FSB, I had to crank the FSB termination voltage for Prime95 in blend mode to not fail with "STOP: 0x00000124" BSOD with "Bus/Interconnect Error" being the reason. That error reason is possibly the most common on 65nm Core 2 Quads.