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Processor | 13th Gen Intel Core i9-13900KS |
---|---|
Motherboard | ASUS ROG Maximus Z790 Apex Encore |
Cooling | Pichau Lunara ARGB 360 + Honeywell PTM7950 |
Memory | 32 GB G.Skill Trident Z5 RGB @ 7600 MT/s |
Video Card(s) | Palit GameRock OC GeForce RTX 5090 32 GB |
Storage | 500 GB WD Black SN750 + 4x 300 GB WD VelociRaptor WD3000HLFS HDDs |
Display(s) | 55-inch LG G3 OLED |
Case | Cooler Master MasterFrame 700 benchtable |
Audio Device(s) | EVGA NU Audio + Sony MDR-V7 headphones |
Power Supply | EVGA 1300 G2 1.3kW 80+ Gold |
Mouse | Microsoft Classic IntelliMouse |
Keyboard | IBM Model M type 1391405 |
Software | Windows 10 Enterprise 22H2 |
Benchmark Scores | I pulled a Qiqi~ |
Similar to your results I've noticed when gaming on my 5950x Windows tends to use the first CCD for gaming and usually little to no activity on the 2nd CCD.
The chiplet architecture Ryzen and EPYC utilize is particular to locality, if you can comport a workload's full demand onto a single CCD and avoid sending data through the infinity fabric or accessing data on cache that is currently residing in an adjacent tile (worst-case scenario), this is what you should do. Of course, that means only the resources locally available to that node are fully exploited. This is essentially why the X3D chips have some degree of trouble on Windows, the OS just sees it as "one big block of available resources" without any regard for their physical location. CCD1 should only be accessed if more resources than CCD0 can provide are requested by the application.
That's why a 8 threaded workload will run better on a 5800X or 5950X as opposed to a 5900X CPU, even though the latter has 12 cores and technically should comport 12 threads just fine. It's because it's 6+6, not 8+0 or 8+8. Zen 3 also did away with the issue that Zen 2 had with the CCXs by making them the same size as the CCD itself, the 3900X was effectively a 3+3+3+3 setup and 3950X 4+4+4+4.
Scroll down a little on this article, there is a huge chart demonstrating both inter-core, inter-CCD and inter-socket access latencies on a Turin system. As you can see, though, there are both memory bandwidth and access latency implications, the same concept also applies to the Ryzen 9's obviously at a much, much smaller scale.