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Arrow Lake Retested with Latest 24H2 Updates and 0x114 Microcode

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Benchmark Scores They're pretty good, nothing crazy.
In an era where 3D cache and memory latency are dominating, Intel's big move seems to have been to put the memory controller on the other side of the processor away from the die.
 
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Very true, the hardware is present, and there are ways to make code with AVX512 instructions not crash on an E core. Maybe MS didn't want to implement, test and support that.
There have been some talk about a software solution to stall threads and move them, but it's probably too optimistic to expect the OS to handle that reliably.
I find it so ridiculous that Intel went ahead and designed this hardware without a proper plan for the most obvious problem. And they could easily have solved it in hardware, have the E-cores use a "double-pumped" version like Zen 4 did, it wouldn't require a lot of extra transistors.

Refining? You mean (potential) security improvements? Because performance wise, the 32-bit mode has been more than good enough for the longest time.
Besides, Intel has just cancelled the X86S project.
They have replaced their x86S project with the x86 ecosystem advisory group, and the effort is expanded, not stopped.
There is also the work with AVX10, hopefully that will be cleaned up in the end.

What kind of security issues on ISA level are you thinking about?
 
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Surprisingly they still haven't appreciably dropped the pricing of it much since launch...

Not like they could do such thing, at least, not to the same extent has AMD...
 
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It's more than clear that Tom's Hardware was right about Arrow Lake suffering from a hardware flaw. Moving memory controller out of compute tile imposes 20-25ns memory penalty and mixing P/E cores (to improve temps) increases L3 cache latency. AMD chiplets handle memory latency better, but not frequencies. Now imagine performance boost that AMD could achieve by moving IMC into tile with cores along with releasing new improved IOD. I'd say Zen 6 does not require any significant changes to core architecture (as introduced with Zen 4 vs. Zen 5) to increase performance, only changes to IMC location and IOD bandwidth are required.

Also, AMD should not drop SMT, as it is delivers much more performance than Intel's HT and produces no power draw increase.
Agreed. I do believe that the new tiled approach that Intel used, while practical, especially when building smaller and larger CPUs, is the main cause of the degraded ARL performance.

Even Zen 5 does suffer from the old IOD/IMC that was reused from Zen 4. But AMD has more experience using tiles, and they made up for a that by having a higher bandwidth cache subsystem, and the much larger L3 cache (on x3d parts).

For Zen 6 (Desktop) I do think that AMD will keep the same IOD/IMC approach but with a:
1. Monolithic 16-Core CCD (2/3nm) and (4nm) IOD/IMC/RDNA3-4. Of course they can add more CCDs for higher end models/Threadripper/Epyc server CPUs etc.
2. All Zen 6 desktop CPUs would have L3 V-Cache (below the CCD tile). And larger L1/L2 on the CCD tile.
a. This approach means that all 16 cores share the same large L3 V-Cache pool (probably at least 128MB)
b. The large V-Cache somewhat mitigates the latency caused by the IOD/IMC being on a separate tile
c. More efficient, practical, and higher performance as all cores share the same L3 cache (no need to worry about which CCD has the V-Cache)
d. AMD can disable some cores/cache for lower SKUs. Example, the same die with 12 cores and 96mb L3 cache, 8 cores and 64mb L3 etc

These are just guesses from my side, but it seems like a good approach that AMD could take.
 

Talon

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Attached here, if that helps. The exe is digitally signed by Intel, and I doubt the ME files will flash if they have been tampered with


Didn't test, no time and no point given these minimal differences

I don't think that is the correct ME version. It's 1854, but you need 1854v2.2. Asus rep stated "Phase 2" beta BIOS will be rolling out soon. 1203 and that version of 1854 ain't it.
 

W1zzard

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I don't think that is the correct ME version. It's 1854, but you need 1854v2.2. Asus rep stated "Phase 2" beta BIOS will be rolling out soon. 1203 and that version of 1854 ain't it.
Aha.. thanks. guess we’ll wait a bit longer for this update then… do you have a link by any chance?
 
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I don't think that is the correct ME version. It's 1854, but you need 1854v2.2. Asus rep stated "Phase 2" beta BIOS will be rolling out soon. 1203 and that version of 1854 ain't it.
Let me add to the confusion, ME firmware is a group of firmwares packaged together, hence it being referred to as a firmware kit by Intel.
I wish they would just show the full firmware list or changelog, what is V2.2? is the update package on the Asus ROG forums already V2.2 or newer?

I could be wrong but AFAIK the main firmware version will just show 19.0.0.1854 no matter if its "v1.0" or "v2.2", I believe that is how it was in older ME versions.

Firmware : 19.0.0.1854 [27/11/2024]
PMC Firmware : 1900.21.0.1054
PCHC Firmware : 1900.21.0.1009
SOCC Firmware : 1900.25.0.1009
ACE Firmware : 20.40.1483.0
PHY S Firmware : 13.0.1.7093
PHY N Firmware : 19.2.0.7014
IOM Firmware : 49.20.0.0
TBT Firmware : 19.0.0.1301
Aha.. thanks. guess we’ll wait a bit longer for this update then… do you have a link by any chance?
@W1zzard Source is Intel itself by looks, probably using the wording field/phase interchangeably. https://community.intel.com/t5/Blog...re-Ultra-200S-Series-Performance/post/1650490

This fifth and final category of performance update requires a new firmware image that is currently undergoing Intel validation prior to customer release. We expect user-facing BIOSes to be released in the first half of January 2025. Exact availability will depend on the test and release schedule for your specific motherboard. The correct BIOSes will be identified with Intel microcode version 0x114 and Intel CSME Firmware Kit 19.0.0.1854v2.2 (or newer).

And old mate Hallock
 
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So basically the combination of everything fixed performance on 24H2 so that is is no longer slower than 23H2.

That's good, and was needed, but obviously does not fix the regression in gaming performance from 14th Gen.
 
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i did buy Intel usualy, even now 13xxx and 14xxx series are great and 13900/14900 are still intel flagship models so very good deal if bought one.

This Ultra series just sux, i sometimes play 1080p mode(med/high settings) and i like to get around 200fps thats not hapenin if using new intel Cpus.
Also Ultra series is overprice
 
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@HueSplat
You seem to be part of the ROG Forum as well. Maybe our forums should merge as like posted in the updated thread a lot of information is already here:
https://rog-forum.asus.com/t5/intel-800-series/arrowlake-resources/td-p/1051570/page/14
And what 'Hallock' concerns I could not listen to him any longer than 1 minute. It's similiar to the experts of Intel Forum. They never answer a question but are always very thankful for asking.
So all in all there is no gain in upgrading what is not that regrettable.
 
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Talon

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i did buy Intel usualy, even now 13xxx and 14xxx series are great and 13900/14900 are still intel flagship models so very good deal if bought one.

This Ultra series just sux, i sometimes play 1080p mode(med/high settings) and i like to get around 200fps thats not hapenin if using new intel Cpus.
Also Ultra series is overprice

What game?
 

raysinbisket

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Doesn't the fact that Intel is matching/beating the 9950X with fewer threads prove the fact that having smaller, carefully designed single-threaded cores provides better results than bigger cores with SMT in fully multi-threaded workloads? Which is exactly my point? Adding little cores that take up less space and power is the way to go for multi-core workloads, and everyone agrees. Yes, AMD still has the same core architecture and HT in their little cores for now, but Intel's showing obvious advantages in changing that by having superior IPC.

And for Intel having to run Windows, you completely ignored my point that Zen had THESE EXACT SAME issues. Radically new CPU architecture provided outstanding multi-thread performance by boosting core count with the dual-CCD design, but faced lots of issues with Windows and apps and games not knowing how to handle thread assignment. Exact same issues Intel is facing now. And those issues haven't even been fully solved yet. As I pointed out, even the Zen 5 launch was compromised by Windows not handling the new architecture properly because 24H2 is trash.

But in hindsight, AMD absolutely made the right choice with Zen and the chiplet design. And in 8 years, I'm sure we're going to look back at 12th gen and Core Ultra and say the same thing about e-cores and removing SMT.
And once again you're missing the point. Sigh.

I'm struggling to see the point you're trying to make? That having more (24) cores perform roughly the same as 33% less (16) is meant to be impressive somehow?

You never remotely addressed my flipping of the statement to talking about cores, and again chose to focus on threads.

For starters, you're comparing E-cores to SMT, which these are not mutually exclusive concepts - they can coexist. Secondly, SMT provides good MT value for die space area, something even Intel discussed when announcing Arrow Lake despite it not having it. SMT largely reuses existing core hardware to implement a second thread, the additional footprint of SMT isn't massive - plus you're more likely to maximise core resource utilisation under SMT. Whereas, adding an E-core is literally just adding an entire extra core.

An SMT thread may not be as strong as an E-core thread, but it also correspondingly takes up much less area than an E-core.

The only sensible justification for removal of SMT/HT from the P-core is if removing it enables optimisation of the architecture which results in better ST, which to be fair I do think we see in ARL.

I don't think anyone is disputing that having high performance and low power/area cores is the way to go, just that Intel has jumped the gun with a solution that Windows isn't designed to take full advantage of.

Plus, Intel's P-cores are so big they literally need E-cores to compete with AMD at all. AMDs standard cores are already reasonably sized, the c cores more so.

The fact that we may end up with a solution in "8 years" that aligns to Intel's approach doesn't change the pitfalls of Intel's approach now.
 
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Honestly, I feel like Intel is getting too much flak for Arrow Lake. While they obviously need to improve things like thread assignment with the new architecture, I feel like most of the blame needs to be assigned to Microsoft. 24H2 is absolutely broken in every single way. Every day a new article comes out about how 24H2 broke a certain feature, or gaming performance, or a software. I work in IT, and we've had to roll back 24H2 on multiple computers because it breaks multiple unrelated pieces of software that are absolutely business-critical for us, so it's not just an issue with a single feature or part of Windows.

I'm very bullish on Intel overall, even with Arrow Lake. The big-little architecture was absolutely the right move for consumers (which AMD immediately copied), they've adopted the chiplet design after seeing how well it worked for AMD (and let AMD handle much of the "teething issues), and they've moving to drop native support for x86, which I think will pair very nicely with moving to single-threaded cores and allow them to simplify core design immensely.
The key concept here is goodwill. Intel has squandered years of goodwill with stagnant products, bad pricing, and a lot of security and quality issues. No one is willing to give Intel a pass anymore. You notice that when AMD has a software issue with Microsoft, AMD usually gets the benefit of the doubt. It is because AMD has more goodwill vs Intel with their Zen products.

Also, I don't let Intel off the hook here. Microsoft has been messing up their software for years now, Intel should have taken this into account either during the product planning process or in the QA process working with Microsoft. The truth is that Intel took some risky business bets, pushed their release ahead in spite of technical issues and problems to meet a marketing deadline, and it all blew up in their face.

Yeah, Intel deserves all the blame it is getting. That is not to excuse Microsoft's incompetence here in any way.
 

raysinbisket

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The key concept here is goodwill. Intel has squandered years of goodwill with stagnant products, bad pricing, and a lot of security and quality issues. No one is willing to give Intel a pass anymore. You notice that when AMD has a software issue with Microsoft, AMD usually gets the benefit of the doubt. It is because AMD has more goodwill vs Intel with their Zen products.

Also, I don't let Intel off the hook here. Microsoft has been messing up their software for years now, Intel should have taken this into account either during the product planning process or in the QA process working with Microsoft. The truth is that Intel took some risky business bets, pushed their release ahead in spite of technical issues and problems to meet a marketing deadline, and it all blew up in their face.

Yeah, Intel deserves all the blame it is getting. That is not to excuse Microsoft's incompetence here in any way.
Also some of the Microsoft related issues were caused by Intel literally setting the go-live date for Windows Updates for Arrow Lake to the consumer launch date rather than a week earlier for reviewers...
 

notoperable

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Public traded corporate body and "goodwill", you sure you teleported into the right Universe?
 
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There have been some talk about a software solution to stall threads and move them, but it's probably too optimistic to expect the OS to handle that reliably.

My opinion: That is the part the scheduler has to do for the kernel. the linux kernel has many changes to that part. A kernel is a part of the operating system.
Months ago I wanted to find specs for those E-Cores. There are none. I just wanted to know which code they can execute and which they can not. From the viewpoint of cpu instructions. I stick to the claim - those E-Cores will not be able to execute my code. If I want to run optimised general purpose i686 code from year ~1995 I can use windows 11 also (please look up when i686 went public ...).
 
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Public traded corporate body and "goodwill", you sure you teleported into the right Universe?
A reply to a post complaining about too much flak going towards a company that mentions goodwill? Yeah, you bet I am in the right universe.
 
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My opinion: That is the part the scheduler has to do for the kernel. the linux kernel has many changes to that part. A kernel is a part of the operating system.
It's not like the scheduler sees what instructions lies ahead, nor which one is executing at this moment. The suggestion I saw mentioned after Alder Lake released was using some kind of detection in the core, stall it, and let the scheduler request to move it. I don't remember the name of the feature, but if its accurate, then it probably didn't work reliably, considering Alder Lake did actually release with AVX-512 enabled you know.

The only software solution I can come up with that would be reliable would be to analyze the binary at launch and scan every page of code for unsupported opcodes, and if so flag the binary for P-core only. But this would probably add a few ms to the launch of any binary, which would lead to horrible performance when launching applications and doing calls to libraries, even with some kind of cache.

Months ago I wanted to find specs for those E-Cores. There are none. I just wanted to know which code they can execute and which they can not. From the viewpoint of cpu instructions.
Have you looked up the Intel® 64 and IA-32 Architectures Optimization Reference Manual?
If there are things developers need to know about Intel archtectures, it should be listed there.

I stick to the claim - those E-Cores will not be able to execute my code. If I want to run optimised general purpose i686 code from year ~1995 I can use windows 11 also (please look up when i686 went public ...).
I'm under the impression that E-cores will run anything except AVX-512 that Alder Lake supports, you can see the compiler targets that Intel themselves have added for GCC. Whether the code runs on E-cores or P-cores should be transparent to the developer.

If you happen to find any information that suggest otherwise, please let me know. I will eventually be getting one of these CPUs myself for the sole purpose of making sure my software detects cores/threads correctly and scale appropriately.
 
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