Have you dug up a proof or at least an indication that the hardware (IOD) supports bifurcation to x2 on any of the PCIe 5.0 lanes?
No, I haven't been researching this topic, but could look around a bit.
MSI manual states that 8500/8300 APUs work in Gen4 x4 (GPU), x4 (M.2_1) and x2 (USB4) configuration, so I'd expect to see a small PCIe switch chip around ASM4242 chip. We can confirm whether this is the case with a photo of the board with IO cover off.
Since low end Zen4 APUs can handle x2 link into USB4 chip, halving PCIe data speed to 32 Gbps over two lanes, it'd be shocking if Granite Ridge IOD on 9950X couldn't do the same.
Both USB4 and M.2_2 pathways connect to the same x4 link on CPU, but each peripheral has four separate lanes of data, as they can operate independently at full speed, if the other one is not used or if it's switched off in BIOS.
To be able to operate together at x2 mode, I'd expect to see a small PCIe switch chip. If this is the case, both could be easily tested in CrystalDisk
A. USB4 speed for PCIe data should be up to 32 Gbps minus overhead, so ~3 GB/s, as ASM4242 would downgrade x2 link from Gen5 to Gen4
B. M.2_2 should operate at the same time at up to 64 Gbps minus overhead, with Gen5 drive installed, so up to ~7 GB/s.
This can be easily tested to confirm, if someone has the board.
It's just the OS trying to communicate with two devices over a single point-to-point link
Both devices should get four physical lanes from a single PHY and can operate at x2 mode too. This suggests that a small switch should be present, so that this could be handled properly.