No, not really.
Intel 14nm transistor size (as measured by crazy German dude):
24 by 24 nm
TSMC 7nm
22 by 22 nm
Link?
How about real world applications. Apple M1, TSMC 5nm, 16 billion transistors, 119mm2 die, density = 135 million transistors per mm2.
AMD Ryzen CCD die, TSMC 7nm, 4.15 billion transistors, die size 80mm2, density = 51 million transistors/mm2.
Intel Ice Lake, Intel 10nm, transistor count estimated to be 7 billion (extrapolated from comments Jim Keller made about the transistor count of an Ice Lake core), die size 122mm2, density = 57 million transistors per mm2.
Subsequent Intel designs??? Who knows, because Intel stopped detailing the transistor count of its cores after Ice Lake, which I think is telling (they had no qualms doing so when they had the density lead over TSMC).
It shows that whilst Intel has previously indicated their OG 10nm process used on Cannonlake was 108million/mm2, the trend since then has been a reduction in density (in order to increase clocks) at the same time TSMC processes have continued to become denser. All indications are that Intel 10ESF is approx equal to TSMC 7nm, and definitely less dense than TSMC 5nm. That still places Intel a full node behind from a transistor density perspective.