Huh. Somebody needs to update Wikipedia then.
Wikipedia is (unsurprisingly) up to date, but you need to compare AMD and Nvidia die sizes on the same node.
AMD were putting out 334mm^2 Cypress dies on 40nm in 2010 when Nvidia's GF100 dies were 529mm^2
For the next node AMD were putting out 352mm^2 Tahiti dies on 28nm when Nvidia's GK110 was 561mm^2
You can
only compare die sizes on the same node, and Wikiepedia is quite clear that AMD's largest dies were significantly smaller than Nvidia's largest dies on each node from that era, hence all the talk of "small die strategy".
Ok, I see what your talking about now. And this goes along with the statement of this should not have been a 5080, but instead a 5070 or 5070ti.
A thought about that, perhaps there's a yield problem at TSMC?
Aye, that was my supporting argument for why this is the true 5070Ti, because it's the exact same rinse-and-repeat as the 40-series launch and
NOBODY accepted the halved 4090 as an 80-class GPU, hence the unlaunch and rebrand to a 4070Ti
As for yields of the 5090, that's not really a TSMC problem, it's just expected when the die size gets this large. For any given process yield, larger dies have exponentially higher chances of defects.
A 4090 is 608mm^2, a 5090 is 750mm^2.
If you put that into a yield calculator you'll get exact numbers, but as a rule of thumb if the die area goes up by 25% like that the chance of a defect goes up by 25%
squared. Nvidia and TSMC keep quiet about exact yields, but estimates say 50-60% yields on the 4090 - meaning 40-50% defect rate. For a 5090, on the same process node, that extra die area means the expected defect rate is 40-50% * 1.25^2 = 62-78%, aka yields of 22-38%, down from 50-60% of the 4090. Hopefully it's not that bad, but these are just estimates based on the process node being identical.
Presumably Nvidia are stockpiling defective dies to have partially-working RTX Blackwell workstation/server compute GPUs that will replace the RTX 5000 and 5880 Ada generation, either that or a 5080Ti down the line.
Could that be L2 cache size not doubled hence the bottleneck?
Or someone could test in native 8K maybe the gap between 5080 and 5090 will widen.
That's not an unreasonable thought, but L2 cache hasn't scaled with core count or core config in forever. I don't know why, that's just my observation.
If I had to guess (and it is a guess), L2 cache would scale with the VRAM bandwidth and total latency, but it doesn't really.