Nanya Technology's Board of Directors today has approved a strategic partnership with PieceMakers Technology, Inc. ("PieceMakers") to jointly develop customized ultra-high-bandwidth memory solutions. As part of the collaboration, Nanya Technology will subscribe to a cash capital increase of up to NT$ 660 million, purchasing up to 22 million common shares at NT$ 30 per share in PieceMakers. Upon completion of the capital increase, Nanya Technology is expected to acquire up to approximately 38% stakes of PieceMakers.

To meet the growing demand for high-performance memory driven by AI and edge computing, this collaboration will combine Nanya Technology's 10 nm-class DRAM innovation with PieceMakers' expertise in customized DRAM design to develop high-value, high-performance, and low-power customized ultra-high-bandwidth memory solutions, unlocking new opportunities in AI and high-performance computing markets.

This week, at the 2024 IEEE International Electron Devices Meeting (IEDM), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, proposes a novel 3D integrated charge-coupled device (CCD) that can operate as a block-addressable buffer memory, in support of data-intensive compute applications. Memory operation is demonstrated on a planar proof-of-concept CCD structure which can store 142 bits. Implementing an oxide semiconductor channel material (such as IGZO) ensures sufficiently long retention time and enables 3D integration in a cost-efficient, 3D NAND-like architecture. Imec expects the 3D CCD memory density to scale far beyond the DRAM limit.

The recent introduction of the compute express link (CXL) memory interface provides opportunities for new memories to complement DRAM in data-intensive compute applications like AI and ML. One example is the CXL type-3 buffer memory, envisioned as an off-chip pool of memories that 'feeds' the various processor cores with large data blocks via a high-bandwidth CXL switch. This class of memories meets different specifications than byte-addressable DRAM, which increasingly struggles to maintain the cost-per-bit-trend scaling line.

Marvell Technology, Inc. (NASDAQ: MRVL), a leader in data infrastructure semiconductor solutions, today announced that it has pioneered a new custom HBM compute architecture that enables XPUs to achieve greater compute and memory density. The new technology is available to all of its custom silicon customers to improve the performance, efficiency and TCO of their custom XPUs. Marvell is collaborating with its cloud customers and leading HBM manufacturers, Micron, Samsung Electronics, and SK hynix to define and develop custom HBM solutions for next-generation XPUs.

HBM is a critical component integrated within the XPU using advanced 2.5D packaging technology and high-speed industry-standard interfaces. However, the scaling of XPUs is limited by the current standard interface-based architecture. The new Marvell custom HBM compute architecture introduces tailored interfaces to optimize performance, power, die size, and cost for specific XPU designs. This approach considers the compute silicon, HBM stacks, and packaging. By customizing the HBM memory subsystem, including the stack itself, Marvell is advancing customization in cloud data center infrastructure. Marvell is collaborating with major HBM makers to implement this new architecture and meet cloud data center operators' needs.

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, today announced that it has pioneered a new custom HBM compute architecture that enables XPUs to achieve greater compute and memory density. The new technology is available to all of its custom silicon customers to improve the performance, efficiency and TCO of their custom XPUs. Marvell is collaborating with its cloud customers and leading HBM manufacturers, Micron, Samsung Electronics, and SK hynix to define and develop custom HBM solutions for next-generation XPUs.

HBM is a critical component integrated within the XPU using advanced 2.5D packaging technology and high-speed industry-standard interfaces. However, the scaling of XPUs is limited by the current standard interface-based architecture. The new Marvell custom HBM compute architecture introduces tailored interfaces to optimize performance, power, die size, and cost for specific XPU designs. This approach considers the compute silicon, HBM stacks, and packaging. By customizing the HBM memory subsystem, including the stack itself, Marvell is advancing customization in cloud data center infrastructure. Marvell is collaborating with major HBM makers to implement this new architecture and meet cloud data center operators' needs.

The Biden-Harris Administration has given Micron Technology up to $6.165 billion in direct funds through the CHIPS Incentives Program to back the company's manufacturing growth. The money will allow Micron to execute its plan announced in October 2022 by investing about $100 billion into Clay, New York fab, and $25 billion into Idaho over 20 years aiming to boost the United States' advanced memory manufacturing from under 2% to around 10% by 2035. This large investment aims to make the U.S. economy stronger by creating a home supply of cutting-edge DRAM chips, moreover it is expected to create approximately 20,000 job across the U.S. Micron plans to spend about $50 billion before 2030 focusing on making more advanced memory semiconductor technology.

Also, the Department of Commerce has put pen to paper on a first draft of terms with Micron. This could lead to funding of up to $275 million to upgrade its Manassas, Virginia plant. The $2 billion investment project aims to bring Micron's 1-alpha technology back to U.S. The 1-alpha process was launched in 2021 and is used for the latest LPDDR5 DRAM chips. This would boost monthly wafer production and create over 400 factory jobs. At its busiest, the project could generate up to 2,700 jobs in the local area.

Kioxia Corporation, a world leader in memory solutions, today announced the development of OCTRAM (Oxide-Semiconductor Channel Transistor DRAM), a new type of 4F2 DRAM, comprised of an oxide-semiconductor transistor that has a high ON current, and an ultra-low OFF current, simultaneously. This technology is expected to realize a low power DRAM by bringing out the ultra-low leakage property of the InGaZnO transistor. This was first announced at the IEEE International Electron Devices Meeting (IEDM) held in San Francisco, CA on December 9, 2024. This achievement was jointly developed by Nanya Technology and Kioxia Corporation. This technology has the potential to lower power consumption in a wide range of applications, including AI and post-5G communication systems, and IoT products.

The OCTRAM utilizes a cylinder-shaped InGaZnO vertical transistor (Fig.1) as a cell transistor. This design enables the adaptation of a 4F2 DRAM, which offers significant advantages in memory density compared to the conventional silicon-based 6F2 DRAM.

During the prestigious IEDM 2024 conference, NVIDIA presented its vision for the future AI accelerator design, which the company plans to chase after in future accelerator iterations. Currently, the limits of chip packaging and silicon innovation are being stretched. However, future AI accelerators might need some additional verticals to gain the required performance improvement. The proposed design at IEDM 24 introduces silicon photonics (SiPh) at the center stage. NVIDIA's architecture calls for 12 SiPh connections for intrachip and interchip connections, with three connections per GPU tile across four GPU tiles per tier. This marks a significant departure from traditional interconnect technologies, which in the past have been limited by the natural properties of copper.

Perhaps the most striking aspect of NVIDIA's vision is the introduction of so-called "GPU tiers"—a novel approach that appears to stack GPU components vertically. This is complemented by an advanced 3D stacked DRAM configuration featuring six memory units per tile, enabling fine-grained memory access and substantially improved bandwidth. This stacked DRAM would have a direct electrical connection to the GPU tiles, mimicking the AMD 3D V-Cache on a larger scale. However, the timeline for implementation reflects the significant technological hurdles that must be overcome. The scale-up of silicon photonics manufacturing presents a particular challenge, with NVIDIA requiring the capacity to produce over one million SiPh connections monthly to make the design commercially viable. NVIDIA has invested in Lightmatter, which builds photonic packages for scaling the compute, so some form of its technology could end up in future NVIDIA accelerators

Global sales of total semiconductor manufacturing equipment by original equipment manufacturers (OEMs) are forecast to set a new industry record, reaching $113 billion in 2024, growing 6.5% year-on-year, SEMI announced today in its Year-End Total Semiconductor Equipment Forecast - OEM Perspective at SEMICON Japan 2024. Semiconductor manufacturing equipment growth is expected to continue in the following years, reaching new records of $121 billion in 2025 and $139 billion in 2026, supported by both the front-end and back-end segments.

"Three consecutive years of projected growth in investments in semiconductor manufacturing reflect the vital role our industry plays in underpinning the global economy and advancing technology innovation," said Ajit Manocha, SEMI president and CEO. "Since our July 2024 forecast, the outlook for 2024 semiconductor equipment sales has brightened, especially with stronger-than-expected investments from China and in AI-related sectors. Together with our forecast extension through 2026, it highlights the robust growth drivers across segments, applications, and regions."

The Biden administration is set to announce new, targeted restrictions on China's semiconductor industry, focusing primarily on emerging chip manufacturing equipment companies rather than broad industry-wide limitations. According to Bloomberg, these new restrictions are supposed to take effect on Monday. The new rules will specifically target two manufacturing facilities owned by Semiconductor Manufacturing International Corp. (SMIC) and will add select companies to the US Entity List, restricting their access to American technology. However, most of Huawei's suppliers can continue their operations, suggesting a more mild strategy. The restrictions will focus on over 100 emerging Chinese semiconductor equipment manufacturers, many of which receive government funding. These companies are developing tools intended to replace those currently supplied by industry leaders such as ASML, Applied Materials, and Tokyo Electron.

The moderated approach comes after significant lobbying efforts from American semiconductor companies, who argued that stricter restrictions could disadvantage them against international competitors. Major firms like Applied Materials, KLA, and Lam Research voiced concerns about losing market share to companies in Japan and the Netherlands, where similar but less stringent export controls are in place. Notably, Japanese companies like SUMCO are already seeing the revenue impacts of Chinese independence. Lastly, the restrictions will have a limited effect on China's memory chip sector. The new measures will not directly affect ChangXin Memory Technologies (CXMT), a significant Chinese DRAM manufacturer capable of producing high-bandwidth memory for AI applications.

Samsung Electronics today announced new leadership for the next phase of the Company's growth and to strengthen its future competitiveness, focusing on the semiconductor business.

Young Hyun Jun, Vice Chairman and Head of Device Solutions (DS) Division, was named CEO and will also become the Head of Memory Business and Samsung Advanced Institute of Technology. Jinman Han was promoted to President and will become the Head of Foundry Business, while Seok Woo Nam will become Chief Technology Officer of Foundry Business, a newly-created position.

TrendForce's latest investigations reveal that the global DRAM industry revenue reached US$26.02 billion in 3Q24, marking a 13.6% QoQ increase. The rise was driven by growing demand for DDR5 and HBM in data centers, despite a decline in LPDDR4 and DDR4 shipments due to inventory reduction by Chinese smartphone brands and capacity expansion by Chinese DRAM suppliers. ASPs continued their upward trend from the previous quarter, with contract prices rising by 8% to 13%, further supported by HBM's displacement of conventional DRAM production.

Looking ahead to 4Q24, TrendForce projects a QoQ increase in overall DRAM bit shipments. However, the capacity constraints caused by HBM production are expected to have a weaker-than-anticipated impact on pricing. Additionally, capacity expansions by Chinese suppliers may prompt PC OEMs and smartphone brands to aggressively deplete inventory to secure lower-priced DRAM products. As a result, contract prices for conventional DRAM and blended prices for conventional DRAM and HBM are expected to decline.

While Intel's primary product focus is on the processors, or brains, that make computers work, system memory (that's DRAM) is a critical component for performance. This is especially true in servers, where the multiplication of processing cores has outpaced the rise in memory bandwidth (in other words, the memory bandwidth available per core has fallen). In heavy-duty computing jobs like weather modeling, computational fluid dynamics and certain types of AI, this mismatch could create a bottleneck—until now.

After several years of development with industry partners, Intel engineers have found a path to open that bottleneck, crafting a novel solution that has created the fastest system memory ever and is set to become a new open industry standard. The recently introduced Intel Xeon 6 data center processors are the first to benefit from this new memory, called MRDIMMs, for higher performance—in the most plug-and-play manner imaginable.

Kioxia Corporation, a world leader in memory solutions, today announced that it has been adopted by Japan's national research and development agency, New Energy and Industrial Technology Development Organization (NEDO), for its groundbreaking proposal on the Development of Manufacturing Technology for Innovative Memory to enhance the post-5G information and communication system infrastructure.

In the post-5G information and communication era, AI is estimated to generate an unprecedented volume of data. This surge will likely escalate the data processing demands of data centers and increase power consumption. To address this, it is crucial that the next-generation memories facilitate rapid data transfer with high-performance processors while increasing capacity and reducing power consumption.

Innodisk, a leading global AI solution provider, announces its DDR5 6400 DRAM series, featuring the industry's largest 64 GB single-module capacity. This 6400 series is purpose-built for data-intensive applications in AI, telehealth, and edge computing, where high performance at the edge is crucial. Available in versatile form factors, including CUDIMM, CSODIMM, and RDIMM, the series delivers unmatched speed, stability, and capacity to meet the rigorous demands of modern edge AI and industrial applications.

The DDR5 6400 series delivers a data transfer rate of 6400 MT/s, offering a 14% boost in speed over previous generations and doubling the maximum capacity to 64 GB. These enhancements make it an optimal choice for applications like Large Language Models (LLMs), generative AI, autonomous vehicles, and mixed reality, which require high-speed, reliable data processing in real time.

TrendForce reports that the focus on HBM products in the DRAM industry is increasingly turning attention toward advanced packaging technologies like hybrid bonding. Major HBM manufacturers are considering whether to adopt hybrid bonding for HBM4 16hi stack products but have confirmed plans to implement this technology in the HBM5 20hi stack generation.

Hybrid bonding offers several advantages when compared to the more widely used micro-bumping. Since it does not require bumps, it allows for more stacked layers and can accommodate thicker chips that help address warpage. Hybrid-bonded chips also benefit from faster data transmission and improved heat dissipation.

Samsung is currently mass-producing its 9th generation V-NAND flash memory chips with 286 layers unveiled this April. According to the Korean Economic Daily, the company targets V-NAND memory chips with at least 400 stacked layers by 2026. In 2013, Samsung became the first company to introduce V-NAND chips with vertically stacked memory cells to maximize capacity. However, stacking beyond 300 levels proved to be a real challenge with the memory chips getting frequently damaged. To address this problem, Samsung is reportedly developing an improved 10th-generation V-NAND that is going to use the Bonding Vertical (BV) NAND technology. The idea is to manufacture the storage and peripheral circuits on separate layers before bonding them vertically. This is a major shift from the current Co-Packaged (CoP) technology. Samsung stated that the new method will increase the density of bits per unit area by 1.6 times (60%), thus leading to increased data speeds.

Samsung's roadmap is truly ambitious, with plans to launch the 11th generation of NAND in 2027 with an estimated 50% improvement in I/O rates, followed by 1,000-layer NAND chips by 2030. Its competitor, SK hynix, is also working on 400-layer NAND aiming to have the technology ready for mass production by the end of 2025, as we previously mentioned in August. Samsung, the current HBM market leader with a 36.9% market share have also plans for its DRAM sector intending to introduce the sixth-generation 10 nm DRAM, or 1c DRAM by the first half of 2025. Then we can expect to see Samsung's seventh-generation 1d nm (still on 10 nm) in 2026, and by 2027 the company hopes to release its first generation sub-10 nm DRAM, or 0a DRAM memory that will use a Vertical Channel Transistor (VCT) 3D structure similar to what NAND flash utilizes.

ASUS Republic of Gamers (ROG) today announced that new ROG Maximus Z890 Apex motherboards have been used to achieve 5 world records, 19 global first-place records and 31 first-place records. In the hands of some of the world's premier professional overclockers, the Maximus Z890 Apex has coaxed dazzling performance out of the latest Intel Core Ultra processor (Series 2) lineup and the latest high-performance memory kits.

Veterans of the overclocking scene will not be surprised to learn that these records were achieved with an Apex motherboard on the bench. This series has an undeniable pedigree. Since the very first model, ASUS has designed Apex motherboards for the singular purpose of helping the world's most talented overclockers shatter barriers on their way to new records.

Kingston Technology Company, Inc., a world leader in memory products, announced the upcoming release of Kingston FURY Renegade DDR5 CUDIMMs, compatible with Intel's new 800-series chipset (formerly codenamed Arrow Lake). Intel's 800-series chipset is the first platform to utilize Clock Drivers on CUDIMMs (Clocked Unbuffered Dual Inline Memory Modules). At 6400 MT/s DDR5, JEDEC mandates the inclusion of a Client Clock Driver (CKD) on UDIMMs and SODIMMs. This component buffers and redrives the clock signal from the processor, enhancing signal integrity to the module. To distinguish these advanced modules from standard DDR5 UDIMMs and SODIMMs, JEDEC has designated them as CUDIMMs and CSODIMMs, respectively.

Kingston FURY Renegade RGB and non-RGB CUDIMM modules start at an overclocked speed of 8400 MT/s and are available as 24 GB single modules and 48 GB dual channel kits. Since CUDIMMs and UDIMMs share the same 288-pin connector, Kingston FURY UDIMMs with XMP and EXPO profiles are also compatible with Intel 800-series motherboards. However, it's recommended to verify compatibility through the motherboard manufacturer's QVL (Qualified Vendor List) or by checking the Kingston Configurator for supported speeds and capacities.

SK hynix Inc. announced today that it recorded 17.5731 trillion won in revenues, 7.03 trillion won in operating profit (with an operating margin of 40%), and 5.7534 trillion won in net profit (with a net margin of 33%) in the third quarter this year. Quarterly revenues marked all-time high, exceeding the previous record of 16.4233 trillion won in the second quarter of this year by more than 1 trillion won. Operating profit and net profit also far exceeded the record of 6.4724 trillion won and 4.6922 trillion won in the third quarter of 2018 during the semiconductor super boom.

SK hynix emphasized that the demand for AI memory continued to be strong centered on data center customers, and the company marked its highest revenue since its foundation by expanding sales of premium products such as HBM and eSSD. In particular, HBM sales showed excellent growth, up more than 70% from the previous quarter and more than 330% from the same period last year.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced upcoming raw card designs currently in development in JEDEC's JC-45 Committee for DRAM Modules in collaboration with the JC-40 and JC-42 Committees. These raw card memory device standards are intended for use in client computing applications such as laptops and desktops and will be supported by related appendix specifications. The forthcoming raw cards will also complement two DDR5 Clock Driver standards published earlier this year: JESD323: DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification and JESD324: DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification.

Integrating a Clock Driver (CKD) into a DDR5 DIMM provides numerous advantages, particularly in memory stability and performance, and enhances signal integrity and reliability at high speeds. By regenerating the clock signal locally on the DIMM, a CKD ensures stable operation even at elevated clock speeds. With a DDR5 CKD, DIMM data rates can be increased from 6400 Mbps to 7200 Mbps in the initial version of the standard, and targeting up to 9200 Mbps in future versions.

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today unveiled industry-first, complete memory interface chipsets for Gen 5 DDR5 RDIMMs and next-generation DDR5 Multiplexed Rank Dual Inline Memory Modules (MRDIMMs). These innovative new products for RDIMMs and MRDIMMs will seamlessly extend DDR5 performance with unparalleled bandwidth and memory capacity for compute-intensive data center and AI workloads.

"The voracious memory demands of AI and HPC require the relentless pursuit of higher performance through continued innovation and technology leadership," said Sean Fan, chief operating officer at Rambus. "With our 30-plus years of renowned high-speed signal integrity and memory system expertise, the Rambus Gen5 RCD, and next-generation MRCD, MDB, and PMIC will be critical enabling chips in future-generation servers leveraging DDR5 RDIMM 8000 and MRDIMM 12800."

Corsair announces broad compatibility across its extensive component ranges designed to realize the potential of the Intel Core Ultra series processors. Intel Core Ultra processors feature a new socket, LGA 1851, and Corsair is ready with a full lineup of compatible CPU coolers. All our CPU coolers compatible with the previous LGA1700 socket are compatible with the new LGA 1851 socket, from our A115 air cooler to our best-performance TITAN RX RGB series of AIO coolers. From our 120 mm single fan radiators to our class-leading 360 mm and 420 mm radiators, we have a solution for you no matter which Core Ultra processor you choose or what case you're using.

To unleash the performance of the new Core Ultra series processors, we have a wide range of DOMINATOR and VENGEANCE series DDR5 memory kits available. These cutting-edge kits are designed to deliver award-winning performance, with XMP certification providing easy overclocking and improved memory bandwidth. Whether you're a gamer, content creator, or professional, Corsair DDR5 memory is the premiere option for reliable high-speed DRAM. With speeds up to 8,200 MT/s and densities up to 128 GB per kit, you can choose from attractive and compact VENGEANCE modules to the aesthetically elite DOMINATOR TITANIUM with RGB lighting that can be controlled through our iCUE software.

TrendForce's latest findings reveal that weaker consumer demand has persisted through 3Q24, leaving AI servers as the primary driver of memory demand. This dynamic, combined with HBM production displacing conventional DRAM capacity, has led suppliers to maintain a firm stance on contract price hikes.

Smartphone brands continue to remain cautious despite some server OEMs continuing to show purchasing momentum. Consequently, TrendForce forecasts that Q4 memory prices will see a significant slowdown in growth, with conventional DRAM expected to increase by only 0-5%. However, benefiting from the rising share of HBM, the average price of overall DRAM is projected to rise 8-13%—a marked deceleration compared to the previous quarter.

Today, Micron updated its corporate logo with new symbolism. The redesign comes as Micron celebrates over four decades of technological advancement in the semiconductor industry. The new logo features a distinctive silicon color, paying homage to the wafers at the core of Micron's products. Its curved lettering represents the company's ability to stay ahead of industry trends and adapt to rapid technological changes. The design also incorporates vibrant gradient colors inspired by light reflections on wafers, which are the core of Mircorn's memory and storage products.

This rebranding effort coincides with Micron's expanding role in AI, where memory and storage innovations are increasingly crucial. The company has positioned itself beyond a commodity memory supplier, now offering leadership in solutions for AI data centers, high-performance computing, and AI-enabled devices. The company has come far from its original 64K DRAM in 1981 to HBM3E DRAM today. Micron offers different HBM memory products, graphics memory powering consumer GPUs, CXL memory modules, and DRAM components and modules.

Samsung Electronics is speeding up its work on 2 nm production facilities, industry sources say. The company has started to install advanced equipment at its "S3" foundry line in Hwaseong to set up a 2 nm production line. This line aims to produce 7,000 wafers each month by the first quarter of next year. Also, Samsung plans to create a 1.4 nm production line at its "S5" foundry in Pyeongtaek Plant 2 by the second quarter of next year. This line has a goal to make 2,000 to 3,000 wafers each month. By the end of next year, Samsung will change all the remaining 3 nm production lines at "S3" to 2 nm.

As we reported earlier, Samsung has pushed back the start date for its Tyler, Texas foundry. The plant set to open by late 2024, won't install equipment until after 2026. Also, Samsung has changed its plans for the Pyeongtaek Fab 4 foundry line. Because of lower demand, it will now make DRAM instead, moreover, at Pyeongtaek Fab 3, which has a 4 nm line, Samsung has cut back production. These changes are part of Samsung's plan to make 2 nm chips next year and 1.4 nm chips by 2027. The company wants to catch up with its rival TSMC, right now, Samsung has 11.5% of the global foundry market in Q2, while TSMC leads with 62.3%. An industry expert stressed how crucial this is saying, "With the delay in 3 nm Exynos production and other issues, getting the 2 nm process right could make or break Samsung Foundry". The struggle for Samsung is real, with the company's top management, led by DS Division Vice Chairman Jeon Young-hyun, having recently issued a public apology for the division's underwhelming performance.